Section 13 8-Bit Timer (TMR)
Channel CKS2
CKS1
TMR_X
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Note:
If the TMR_Y clock input is set as the TCNT_X overflow signal and the TMR_X clock
*
input is set as the TCNT_Y compare-match signal simultaneously, a count-up clock
cannot be generated. These settings should not be made.
[Legend]
x:
Don't care
:
Invalid
Rev. 3.00 Jul. 14, 2005 Page 388 of 986
REJ09B0098-0300
TCR
CKS0
CKSX
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
1
1
1
0
1
1
x
0
x
1
x
TCRXY
Description
CKSY
—
Disables clock input
Increments at φ
—
Increments at φ/2
—
Increments at φ/4
—
—
Disables clock input
—
Disables clock input
Increments at φ/2048
—
Increments at φ/4096
—
Increments at φ/8192
—
—
Increments at compare-match A from
TCNT_Y*
—
Increments at rising edge of external
clock
—
Increments at falling edge of external
clock
—
Increments at both rising and falling
edges of external clock