Time Constant Register B (Tcorb); Timer Control Register (Tcr) - Renesas H8S Series Hardware Manual

Section 13 8-Bit Timer (TMR)
13.3.3

Time Constant Register B (TCORB)

TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 (or TCORB_X and
TCORB_Y) comprise a single 16-bit register, so they can be accessed together by word access.
TCORB is continually compared with the value in TCNT. When a match is detected, the
corresponding compare-match flag B (CMFB) in TCSR is set to 1. Note however that comparison
is disabled during the T
freely controlled by these compare-match B signals and the settings of output select bits OS3 and
OS2 in TCSR. TCORB is initialized to H'FF.
13.3.4

Timer Control Register (TCR)

TCR selects the TCNT clock source and the condition by which TCNT is cleared, and
enables/disables interrupt requests.
Bit Bit Name Initial Value R/W Description
7 CMIEB 0
6 CMIEA 0
5 OVIE 0
Rev. 3.00 Jul. 14, 2005 Page 384 of 986
REJ09B0098-0300
state of a TCORB write cycle. The timer output from the TMO pin can be
2
R/W Compare-Match Interrupt Enable B
Selects whether the CMFB interrupt request (CMIB) is
enabled or disabled when the CMFB flag in TCSR is set to
1.
0: CMFB interrupt request (CMIB) is disabled
1: CMFB interrupt request (CMIB) is enabled
R/W Compare-Match Interrupt Enable A
Selects whether the CMFA interrupt request (CMIA) is
enabled or disabled when the CMFA flag in TCSR is set to
1.
0: CMFA interrupt request (CMIA) is disabled
1: CMFA interrupt request (CMIA) is enabled
R/W Timer Overflow Interrupt Enable
Selects whether the OVF interrupt request (OVI) is enabled
or disabled when the OVF flag in TCSR is set to 1.
0: OVF interrupt request (OVI) is disabled
1: OVF interrupt request (OVI) is enabled