External Trigger Input Timing; Figure 19.3 External Trigger Input Timing; Table 19.3 A/D Conversion Time (Single Mode) - Renesas H8S Series Hardware Manual

Section 19 A/D Converter

Table 19.3 A/D Conversion Time (Single Mode)

Item
A/D conversion start delay time
Input sampling time
A/D conversion time
Notes: Values in the table indicate the number of states.
* in the table indicates that the system clock (φ) is 16 MHz or lower.
19.4.4

External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in
ADCR, an external trigger is input to the ADTRG pin. The ADST bit in ADCSR is set to 1 at the
falling edge of the ADTRG pin, thus starting A/D conversion. Other operations, in both single and
scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 19.3 shows
the timing.
φ
ADTRG
Internal trigger
signal
ADST
Rev. 3.00 Jul. 14, 2005 Page 726 of 986
REJ09B0098-0300
Symbol
t
D
t
SPL
t
CONV

Figure 19.3 External Trigger Input Timing

CKS = 0
Min. Typ. Max.

10 17
 
63

259 266
A/D conversion
CKS = 1*
Min. Typ. Max.

6 9
 
31

131 134