Keyboard Control Register L (Kbcrl) - Renesas H8S Series Hardware Manual

Section 17 Keyboard Buffer Control Unit (KBU)
17.3.4

Keyboard Control Register L (KBCRL)

KBCRL enables the receive counter count and controls the keyboard buffer control unit pin
output.
Bit Bit Name Initial Value
7 KBE 0
6 KCLKO 1
5 KDO 1
4 — 1
Rev. 3.00 Jul. 14, 2005 Page 590 of 986
REJ09B0098-0300
R/W Description
R/W Keyboard Enable
Enables or disables loading of receive data into KBBR.
0: Loading of receive data into KBBR is disabled
1: Loading of receive data into KBBR is enabled
R/W Keyboard Clock Out
Controls KBU clock I/O pin output.
0: KBU clock I/O pin is low
1: KBU clock I/O pin is high
R/W Keyboard Data Out
Controls KBU data I/O pin output.
0: KBU data I/O pin is low
1: KBU data I/O pin is high
When the start bit (KDO) is automatically cleared (KDO
= 1) by means of automatic transmission, 0 is written
after reading 1.
— Reserved
This bit is always read as 1 and cannot be modified.