Renesas H8S Series Hardware Manual page 690

Section 18 LPC Interface (LPC)
Bit Bit Name Initial Value Slave Host Description
3 SMIE3A 0
2 SMIE2 0
Rev. 3.00 Jul. 14, 2005 Page 642 of 986
REJ09B0098-0300
R/W

R/W Host SMI Interrupt Enable 3A
Enables or disables an SMI interrupt request when
OBF3A is set by an ODR3 write.
0: Host SMI interrupt request by OBF3A and
SMIE3A is disabled
[Clearing conditions]
•
Writing 0 to SMIE3A
•
LPC hardware reset, LPC software reset
•
Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
Host SMI interrupt request by setting is enabled
[When IEDIR3 = 1]
Host SMI interrupt is requested
[Setting condition]
•
Writing 1 after reading SMIE3A = 0

R/W Host SMI Interrupt Enable 2
Enables or disables an SMI interrupt request when
OBF2 is set by an ODR2 write.
0: Host SMI interrupt request by OBF2 and SMIE2 is
disabled
[Clearing conditions]
•
Writing 0 to SMIE2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR2 = 0)
1: [When IEDIR2 = 0]
Host SMI interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR2 = 1]
Host SMI interrupt is requested
[Setting condition]
•
Writing 1 after reading SMIE2 = 0