Renesas H8S Series Hardware Manual page 35

Figure 12.51 Conflict between Buffer Register Write and Input Capture .................................. 374
Figure 12.52 Conflict between Overflow and Counter Clearing ................................................ 375
Figure 12.53 Conflict between TCNT Write and Overflow ....................................................... 376
Section 13 8-Bit Timer (TMR)
Figure 13.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)............................................ 379
Figure 13.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X) .......................................... 380
Figure 13.3 Pulse Output Example ............................................................................................. 397
Figure 13.4 Count Timing for Internal Clock Input.................................................................... 398
Figure 13.5 Count Timing for External Clock Input (Both Edges) ............................................ 398
Figure 13.6 Timing of CMF Setting at Compare-Match ............................................................ 399
Figure 13.7 Timing of Toggled Timer Output by Compare-Match A Signal............................. 399
Figure 13.8 Timing of Counter Clear by Compare-Match ......................................................... 400
Figure 13.9 Timing of Counter Clear by External Reset Input................................................... 400
Figure 13.10 Timing of OVF Flag Setting.................................................................................. 401
Figure 13.11 Timing of Input Capture Operation ....................................................................... 404
Figure 13.12 Timing of Input Capture Signal
(Input capture signal is input during TICRR and TICRF read) ............................. 405
Figure 13.13 Conflict between TCNT Write and Clear.............................................................. 407
Figure 13.14 Conflict between TCNT Write and Count-Up....................................................... 408
Figure 13.15 Conflict between TCOR Write and Compare-Match ............................................ 409
Section 14 Watchdog Timer (WDT)
Figure 14.1 Block Diagram of WDT .......................................................................................... 414
Figure 14.2 Watchdog Timer Mode (RST/NMI = 1) Operation................................................. 421
Figure 14.3 Interval Timer Mode Operation............................................................................... 421
Figure 14.4 OVF Flag Set Timing .............................................................................................. 422
Figure 14.5 Output Timing of RESO signal ............................................................................... 422
Figure 14.6 Writing to TCNT and TCSR (WDT_0)................................................................... 424
Figure 14.7 Conflict between TCNT Write and Increment ........................................................ 425
Figure 14.8 Sample Circuit for Resetting the System by the RESO Signal................................ 426
Section 15 Serial Communication Interface (SCI, IrDA)
Figure 15.1 Block Diagram of SCI............................................................................................. 429
Figure 15.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits) .................................................. 455
Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 457
Figure 15.4 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode) ............................................................................................. 458
Figure 15.5 Sample SCI Initialization Flowchart ....................................................................... 459
Figure 15.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 460
Rev. 3.00 Jul. 14, 2005 Page xxxv of xlviii