Figure 16.15 Example Of Master Receive Mode Operation Timing (Mls = Ackb = 0, Wait = 1); Figure 16.16 Example Of Stop Condition Issuance Timing In Master Receive Mode (Mls = Ackb = 0, Wait = 1) - Renesas H8S Series Hardware Manual

2
Section 16 I C Bus Interface (IIC)
Master tansmit mode
SCL
(master output) 9
SDA A
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
User processing
[1] TRS cleared to 0
IRIC cleard to 0
Figure 16.15 Example of Master Receive Mode Operation Timing
SCL
8
(master output)
SDA
Bit 0
(slave output)
Data 2 [3]
SDA
(master output)
IRIC
IRTR
[4] IRTR=0
ICDR Data 1
User processing
[6] IRIC clear
(to end wait
insertion)
Figure 16.16 Example of Stop Condition Issuance Timing in Master Receive Mode
Rev. 3.00 Jul. 14, 2005 Page 550 of 986
REJ09B0098-0300
Master receive mode
1 2 3 4
Bit 7 Bit 6 Bit 5 Bit 4
Data 1
[2] ICDR read
(dummy read)
(MLS = ACKB = 0, WAIT = 1)
[8] Wait for one clock pulse
9
1 2 3
Bit 6 Bit 5
Bit 7
Data 3
[3]
A
[4] IRTR=1
[11] IRIC clear
[10] ICDR read (Data 2)
[9] Set TRS=1
[7] Set ACKB=1
(MLS = ACKB = 0, WAIT = 1)
5 6 7 8
Bit 3 Bit 2 Bit 1 Bit 0
[3]
[4]IRTR=0
[6] IRIC clear
(to end wait insertion)
7
4 5 6 8
Bit 4 Bit 2
Bit 3 Bit 1 Bit 0
Data 2
[14] IRIC clear
9 1 2 3
Bit 7 Bit 6 Bit 5
Data 2
[3]
A
[4] IRTR=1
Data 1
[5] ICDR read [6] IRIC clear
(Data 1)
Stop condition generation
9
[12]
[12]
A
[13] IRTR=1
[13] IRTR=0
Data 3
[15] WAIT cleared
to 0, IRIC clear
(to end wait
[17] Stop condition
insertion)
issuance
[16] ICDR read
4 5
Bit 4 Bit 3
(Data 3)