Renesas H8S Series Hardware Manual page 32

Figure 5.5 Block Diagram of Interrupts KIN15 to KIN0 and WUE15 to WUE0
(Example of WUE15 to WUE8)................................................................................ 101
Figure 5.6 Block Diagram of Interrupt Control Operation ......................................................... 110
Figure 5.7 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 .... 113
Figure 5.8 State Transition in Interrupt Control Mode 1 ............................................................ 114
Figure 5.9 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1 .... 116
Figure 5.10 Interrupt Exception Handling.................................................................................. 118
Figure 5.11 Interrupt Control for DTC ....................................................................................... 120
Figure 5.12 Block Diagram of Address Break Function ............................................................ 122
Figure 5.13 Examples of Address Break Timing........................................................................ 124
Figure 5.14 Conflict between Interrupt Generation and Disabling............................................. 125
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of BSC ............................................................................................. 129
Section 7 Data Transfer Controller (DTC)
Figure 7.1 Block Diagram of DTC ............................................................................................. 136
Figure 7.2 Block Diagram of DTC Activation Source Control .................................................. 143
Figure 7.3 DTC Register Information Location in Address Space............................................. 144
Figure 7.4 DTC Operation Flowchart......................................................................................... 147
Figure 7.5 Memory Mapping in Normal Mode .......................................................................... 148
Figure 7.6 Memory Mapping in Repeat Mode ........................................................................... 149
Figure 7.7 Memory Mapping in Block Transfer Mode .............................................................. 150
Figure 7.8 Chain Transfer Operation.......................................................................................... 151
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ..................... 152
Figure 7.10 DTC Operation Timing
(Example of Block Transfer Mode, with Block Size of 2) ..................................... 153
Figure 7.11 DTC Operation Timing (Example of Chain Transfer) ............................................ 153
Section 8 I/O Ports
Figure 8.1 Noise Cancel Circuit ................................................................................................. 184
Figure 8.2 Noise Cancel Operation ............................................................................................ 184
Section 9 8-Bit PWM Timer (PWM)
Figure 9.1 Block Diagram of PWM Timer................................................................................. 248
Figure 9.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000) ..... 255
Figure 9.3 Example of PWM Setting.......................................................................................... 256
Figure 9.4 Example when PWM is Used as D/A Converter....................................................... 256
Section 10 14-Bit PWM Timer (PWMX)
Figure 10.1 PWMX (D/A) Block Diagram ................................................................................ 259
Figure 10.2 (1) DACNT Access Operation (1) [CPU → DACNT(H'AA57) Writing] .............. 267
Figure 10.2 (2) DACNT Access Operation (2) [DACNT → CPU(H'AA57) Reading].............. 268
Rev. 3.00 Jul. 14, 2005 Page xxxii of xlviii