Figure 12.42 Timing For Status Flag Clearing By Cpu; Figure 12.43 Timing For Status Flag Clearing By Dtc Activation - Renesas H8S Series Hardware Manual

(4) Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is
activated, the flag is cleared automatically. Figure 12.42 shows the timing for status flag clearing
by the CPU, and figure 12.43 shows the timing for status flag clearing by the DTC.
φ
Address
Write signal
Status flag
Interrupt
request
signal

Figure 12.42 Timing for Status Flag Clearing by CPU

φ
Address
Status flag
Interrupt
request
signal

Figure 12.43 Timing for Status Flag Clearing by DTC Activation

Section 12 16-Bit Timer Pulse Unit (TPU)
TSR write cycle
T1 T2
TSR address
DTC DTC
read cycle write cycle
T1 T2 T1
Destination
Source address
address
Rev. 3.00 Jul. 14, 2005 Page 367 of 986
T2
REJ09B0098-0300