Usage Notes; Table 16.9 I 2 C Bus Timing (Scl And Sda Outputs) - Renesas H8S Series Hardware Manual

2
Section 16 I C Bus Interface (IIC)
16.6

Usage Notes

1. In master mode, if an instruction to generate a start condition is issued and then an instruction
to generate a stop condition is issued before the start condition is output to the I
condition will be output correctly. To output the stop condition followed by the start
condition*, after issuing the instruction that generates the start condition, read DR in each I
bus output pin, and check that SCL and SDA are both low. The pin states can be monitored by
reading DR even if the ICE bit is set to 1. Then issue the instruction that generates the stop
condition. Note that SCL may not yet have gone low when BBSY is cleared to 0.
Note: * An illegal procedure in the I
2. Either of the following two conditions will start the next transfer. Pay attention to these
conditions when accessing to ICDR.
 Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
ICDRS)
 Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
ICDRR)
3. Table 16.9 shows the timing of SCL and SDA outputs in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
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Table 16.9 I C Bus Timing (SCL and SDA Outputs)
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
Note: 6t when IICX is 0, 12t
*
cyc
Rev. 3.00 Jul. 14, 2005 Page 570 of 986
REJ09B0098-0300
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C bus specification.
Symbol Output Timing
t 28t
SCLO
t 0.5t
SCLHO
t 0.5t
SCLLO
t 0.5t
BUFO
t 0.5t
STAHO
t 1t
STASO
t 0.5t
STOSO
t 1t
SDASO
1t
12t
t 3t
SDAHO
when 1.
cyc
Unit
to 256t ns
cyc cyc
ns
SCLO
ns
SCLO
– 1t ns
SCLO cyc
– 1t ns
SCLO cyc
ns
SCLO
+ 2t ns
SCLO cyc
– 3t ns
SCLLO cyc
– (6t or
SCLL cyc
*)
cyc
ns
cyc
2
C bus, neither
2
C
Notes
See figure
26.23