Renesas H8S Series Hardware Manual page 18
16-bit single-chip microcomputer
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Also See for H8S Series:
- Hardware manual (1047 pages) ,
- User manual (38 pages) ,
- User manual (21 pages)
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Section 10 14-Bit PWM Timer (PWMX) ......................................................... 259
10.1 Features.............................................................................................................................. 259
10.2 Input/Output Pins............................................................................................................... 260
10.3 Register Descriptions......................................................................................................... 260
10.3.1 PWMX (D/A) Counter (DACNT) ........................................................................ 261
10.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB) ......................... 262
10.3.3 PWMX (D/A) Control Register (DACR) ............................................................. 264
10.3.4 Peripheral Clock Select Register (PCSR) ............................................................. 265
10.4 Bus Master Interface.......................................................................................................... 266
10.5 Operation ........................................................................................................................... 269
10.6 Usage Notes ....................................................................................................................... 276
10.6.1 Module Stop Mode Setting ................................................................................... 276
Section 11 16-Bit Free-Running Timer (FRT).................................................. 277
11.1 Features.............................................................................................................................. 277
11.2 Input/Output Pins............................................................................................................... 279
11.3 Register Descriptions......................................................................................................... 279
11.3.1 Free-Running Counter (FRC) ............................................................................... 280
11.3.2 Output Compare Registers A and B (OCRA and OCRB) .................................... 280
11.3.3 Input Capture Registers A to D (ICRA to ICRD) ................................................. 280
11.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF) .......................... 281
11.3.5 Output Compare Register DM (OCRDM)............................................................ 281
11.3.6 Timer Interrupt Enable Register (TIER)............................................................... 282
11.3.7 Timer Control/Status Register (TCSR)................................................................. 283
11.3.8 Timer Control Register (TCR).............................................................................. 286
11.3.9 Timer Output Compare Control Register (TOCR) ............................................... 287
11.4 Operation ........................................................................................................................... 289
11.4.1 Pulse Output ......................................................................................................... 289
11.5 Operation Timing............................................................................................................... 290
11.5.1 FRC Increment Timing......................................................................................... 290
11.5.2 Output Compare Output Timing........................................................................... 291
11.5.3 FRC Clear Timing ................................................................................................ 291
11.5.4 Input Capture Input Timing .................................................................................. 292
11.5.5 Buffered Input Capture Input Timing ................................................................... 293
11.5.6 Timing of Input Capture Flag (ICF) Setting ......................................................... 294
11.5.7 Timing of Output Compare Flag (OCF) setting.................................................... 295
11.5.8 Timing of FRC Overflow Flag Setting ................................................................. 295
11.5.9 Automatic Addition Timing.................................................................................. 296
11.5.10 Mask Signal Generation Timing........................................................................... 297
Rev. 3.00 Jul. 14, 2005 Page xviii of xlviii
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