On-Chip Ram Protect Control Register (Mpcr); User Command Register (Ucmdtr) - Renesas H8S Series Hardware Manual

Section 18 LPC Interface (LPC)

18.3.30 On-Chip RAM Protect Control Register (MPCR)

MPCR controls the access to the on-chip RAM in LPC/FW memory RW cycles. The contents of
this register must not be changed in LPC/FW memory cycles (while LMCE is set to 1).
Bit Bit Name Initial Value Slave Host Description
7 to 2 
All 0
1 RAMWE 0
0 RAMRE 0

18.3.31 User Command Register (UCMDTR)

UCMDTR stores the user command data on user command reception.
Bit Bit Name Initial Value Slave Host Description
7 bit7 0
6 bit6 0
5 bit5 0
4 bit4 0
3 bit3 0
2 bit2 0
1 bit1 0
0 bit0 0
Rev. 3.00 Jul. 14, 2005 Page 676 of 986
REJ09B0098-0300
R/W

R/W Reserved

R/W On-Chip RAM Write Access Enable
Enables/disables the access to the on-chip RAM in
LPC/FW memory write cycles.
0: Access inhibited
1: Access enabled

R/W On-Chip RAM Read Access Enable
Enables/disables the access to the on-chip RAM in
LPC/FW memory read cycles.
0: Access inhibited
1: Access enabled
R/W
R W User Command Data
R W Writing operation with the user command
R W
R W
R W
R W
R W
R W