Figure 16.24 Example Of Slave Transmit Mode Operation Timing (Mls = 0) - Renesas H8S Series Hardware Manual

10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL
is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the
STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to
0.
Slave receive mode
SCL
(master output) 8 9
SDA
(slave output)
A
[2]
SDA
(master output)
R/W
IRIC
ICDRE
ICDR
User processing
Figure 16.24 Example of Slave Transmit Mode Operation Timing
1 2
Bit 7 Bit 6
[3] IRIC clear
[3] ICDR write
[3] IRIC clear
(MLS = 0)
Slave transmit mode
3 4 5 6
Bit 5 Bit 4 Bit 3 Bit 2
Data 1
Data 1
Rev. 3.00 Jul. 14, 2005 Page 561 of 986
2
Section 16 I C Bus Interface (IIC)
7 8 9
Bit 1 Bit 0 Bit 7
[4]
A
Data 2
[5] ICDR write
REJ09B0098-0300
1 2
Bit 6
Data 2
[5] IRIC clear