Host Interface Control Registers 0 And 1 (Hicr0 And Hicr1) - Renesas H8S Series Hardware Manual

18.3.1

Host Interface Control Registers 0 and 1 (HICR0 and HICR1)

HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits
that determine pin output and the internal state of the LPC interface, and status flags that monitor
the internal state of the LPC interface.
• HICR0
Bit Bit Name Initial Value Slave Host Description
7 LPC3E 0
6 LPC2E 0
5 LPC1E
0
R/W

R/W LPC Enables 3 to 1

R/W Enable or disable the LPC interface function. When
the LPC interface is enabled (one of the three bits is

R/W
set to 1), processing for data transfer between the
slave (this LSI) and the host is performed using pins
LAD3 to LAD0, LFRAME, LRESET, LCLK, SERIRQ,
CLKRUN, and LPCPD.
•
LPC3E
0: LPC channel 3 operation is disabled
No address (LADR3) matches for IDR3, ODR3,
STR3, or TWR0 to TWR15
1: LPC channel 3 operation is enabled
•
LPC2E
0: LPC channel 2 operation is disabled
No address (H'0062, 66) matches for IDR2,
ODR2, or STR2
1: LPC channel 2 operation is enabled
•
LPC1E
0: LPC channel 1 operation is disabled
No address (H'0060, 64) matches for IDR1,
ODR1, or STR1
1: LPC channel 1 operation is enabled
Section 18 LPC Interface (LPC)
Rev. 3.00 Jul. 14, 2005 Page 619 of 986
REJ09B0098-0300