Clock; Figure 15.4 Relation Between Output Clock And Transmit Data Phase (Asynchronous Mode) - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

Hide thumbs Also See for H8S Series:

Table of Contents

Section 15 Serial Communication Interface (SCI, IrDA)

Clock

Either an internal clock generated by the on-chip baud rate generator or an external clock input at

the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in

SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the

clock frequency should be 16 times the bit rate used.

When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The

frequency of the clock output in this case is equal to the bit rate, and the phase is such that the

rising edge of the clock is in the middle of the transmit data, as shown in figure 15.4.

Figure 15.4 Relation between Output Clock and Transmit Data Phase

Rev. 3.00 Jul. 14, 2005 Page 458 of 986

REJ09B0098-0300

(Asynchronous Mode)

H8s/2100 series H8s/2114r R4f2114r