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10.10
Usage Notes
10.10.1 Conflict between TCNT Write and Counter Clear
If a counter clear signal is generated during the T
10.14, clearing takes priority and the counter write is not performed.
φ
Address
Internal write signal
Counter clear signal
TCNT
Note: * TMR_A, TMR_B
Figure 10.14 Conflict between TCNT Write and Clear
10.10.2 Conflict between TCNT Write and Count-Up
If a count-up occurs during the T
counter write takes priority and the counter is not incremented.
φ
Address
Internal write signal
TCNT input clock
TCNT
Note: * TMR_A, TMR_B
Figure 10.15 Conflict between TCNT Write and Count-Up
Rev. 1.00, 05/04, page 216 of 544
state of a TCNT write cycle as shown in figure
2
TCNT write cycle by CPU
T
1
TCNT address
N
state of a TCNT write cycle as shown in figure 10.15, the
2
TCNT write cycle by CPU
T
1
TCNT address
N
Counter write data
T
T
*
2
3
H'00
T
T
*
2
3
M
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