Internal Block Diagram; Figure 1.1 H8S/2114R Group Internal Block Diagram - Renesas H8S Series Hardware Manual

1.2

Internal Block Diagram

VCC
VCC
VCC
VCL
VSS
VSS
VSS
VSS
VSS
X1
X2
RES
XTAL
EXTAL
MD2
MD1
MD0
FWE
NMI
STBY
RESO
ETRST
PE0/LID3
PE1*/ETCK
PE2*/ETDI
PE3*/ETDO
PE4*/ETMS
P90 /IRQ2/ADTRG
P91/IRQ1
P92/IRQ0
P93/IRQ12
P94/IRQ13
P95/IRQ14
P96/φ/EXCL
P97/IRQ15/SDA0
P60/KIN0/FTCI/TMIX
P61/KIN1/FTOA
P62/KIN2/FTIA/TMIY
P63/KIN3/FTIB
P64/KIN4/FTIC
P65/KIN5/FTID
P66/IRQ6/KIN6/FTOB
P67/IRQ7/KIN7/TMOX
P40/TMCI0/TxD2/DSERIRQ
P41/TMO0/RxD2/DCLKRUN
P42/ExIRQ7/TMRI0/SCK2/SDA1
P43/TMCI1
P44/TMO1
P45/TMRI1
P46/PWX0
P47/PWX1
P80/PME
P81/GA20
P82/CLKRUN
P83/LPCPD
P84/IRQ3/TxD1/IrTxD
P85/IRQ4/RxD1/IrRxD
P86/IRQ5/SCK1/SCL1
Note: * Not supported by the system development tool (emulator).

Figure 1.1 H8S/2114R Group Internal Block Diagram

Clock pulse
H8S/2000CPU
generator
DTC
ROM
(flash memory)
LPC
RAM
Interrupt
controller
WDT × 2 channels
16-bit FRT
8-bit timer
KBU × 3 channels
× 4 channels
SCI × 2 channels
(IrDA × 1 channel)
14-bit PWM
IIC × 2 channels
× 2 channels
10-bit A/D converter
Boundary scan
TPU × 3 channels
(JTAG)
Port 7 Port G
8-bit PWM
Port C
Rev. 3.00 Jul. 14, 2005 Page 3 of 986
Section 1 Overview
PA0/KIN8
PA1/KIN9
PA2/KIN10/PS2AC
PA3/KIN11/PS2AD
PA4/KIN12/PS2BC
PA5/KIN13/PS2BD
PA6/KIN14/PS2CC
PA7/KIN15/PS2CD
P20/PW8
P21/PW9
P22/PW10
P23/PW11
P24/PW12
P25/PW13
P26/PW14
P27/PW15
P10
P11
P12
P13
P14
P15
P16
P17
P30/LAD0
P31/LAD1
P32/LAD2
P33/LAD3
P34/LFRAME
P35/LRESET
P36/LCLK
P37/SERIRQ
PB0/WUE0/LSMI
PB1/WUE1/LSCI
PB2/WUE2
PB3/WUE3/DLFRAME
PB4/WUE4/DLAD3
PB5/WUE5/DLAD2
PB6/WUE6/DLAD1
PB7/WUE7/DLAD0
P50/ExEXCL
P51/TMOY
P52/ExIRQ6/SCL0
PD0/TIOCA0
PD1/TIOCB0
PD2/TIOCC0/TCLKA
PD3/TIOCD0/TCLKB
PD4/TIOCA1
PD5/TIOCB1/TCLKC
PD6/TIOCA2
PD7/TIOCB2/TCLKD
PF0/IRQ8
PF1/IRQ9
PF2/IRQ10
PF3/IRQ11/ExTMOX
PF4/ExPW12
PF5/ExPW13
PF6/ExPW14
PF7/ExPW15
REJ09B0098-0300