10.10.11 Contention Between Overflow/Underflow And Counter Clearing; Figure 10.51 Contention Between Buffer Register Write And Input Capture; Figure 10.52 Contention Between Overflow And Counter Clearing - Renesas H8S/2368 Series Hardware Manual

φ
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register

Figure 10.51 Contention between Buffer Register Write and Input Capture

10.10.11 Contention between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 10.52 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
TCNT input
clock
TCNT
Counter
clearing signal
TGF
TCFV

Figure 10.52 Contention between Overflow and Counter Clearing

Rev. 2.00, 05/03, page 450 of 820
Buffer register write cycle
T
Buffer register
M
φ
H'FFFF
Disabled
T
1 2
address
N
N
M
H'0000