Timer Interrupt Enable Register (Tier) - Renesas H8S Series Hardware Manual

Section 11 16-Bit Free-Running Timer (FRT)
11.3.6

Timer Interrupt Enable Register (TIER)

TIER enables and disables interrupt requests.
Bit Bit Name Initial Value
7 ICIAE 0
6 ICIBE 0
5 ICICE 0
4 ICIDE 0
3 OCIAE 0
Rev. 3.00 Jul. 14, 2005 Page 282 of 986
REJ09B0098-0300
R/W Description
R/W Input Capture Interrupt A Enable
Selects whether to enable input capture interrupt A
request (ICIA) when input capture flag A (ICFA) in
TCSR is set to 1.
0: ICIA requested by ICFA is disabled
1: ICIA requested by ICFA is enabled
R/W Input Capture Interrupt B Enable
Selects whether to enable input capture interrupt B
request (ICIB) when input capture flag B (ICFB) in
TCSR is set to 1.
0: ICIB requested by ICFB is disabled
1: ICIB requested by ICFB is enabled
R/W Input Capture Interrupt C Enable
Selects whether to enable input capture interrupt C
request (ICIC) when input capture flag C (ICFC) in
TCSR is set to 1.
0: ICIC requested by ICFC is disabled
1: ICIC requested by ICFC is enabled
R/W Input Capture Interrupt D Enable
Selects whether to enable input capture interrupt D
request (ICID) when input capture flag D (ICFD) in
TCSR is set to 1.
0: ICID requested by ICFD is disabled
1: ICID requested by ICFD is enabled
R/W Output Compare Interrupt A Enable
Selects whether to enable output compare interrupt A
request (OCIA) when output compare flag A (OCFA) in
TCSR is set to 1.
0: OCIA requested by OCFA is disabled
1: OCIA requested by OCFA is enabled