Second Slave Address Register (Sarx) - Renesas H8S Series Hardware Manual

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Section 16 I C Bus Interface (IIC)
16.3.3

Second Slave Address Register (SARX)

SARX sets the second slave address and selects the communication format. If the LSI is in slave
mode, when received address matches the second slave address, transmission/reception using the
DTC is enabled. If the LSI is in slave mode with the I
set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start
condition, the LSI operates as the slave device specified by the master device. SARX can be
accessed only when the ICE bit in ICCR is cleared to 0.
Bit Bit Name Initial Value R/W
7 SVAX6 0
6 SVAX5 0
5
SVAX4 0
4 SVAX3 0
3 SVAX2 0
2 SVAX1 0
1 SVAX0 0
0 FSX 1
Rev. 3.00 Jul. 14, 2005 Page 512 of 986
REJ09B0098-0300
Description
R/W Second Slave Address 6 to 0
R/W Set the second slave address.
R/W
R/W
R/W
R/W
R/W
R/W Format Select X
Selects the communication format together with the FS bit
in SAR. See table 16.2.
2
C bus format selected, when the FSX bit is