Renesas H8S Series Hardware Manual page 689

Bit Bit Name Initial Value Slave Host Description
6 SELREQ 0
5 IEDIR2 0
4 SMIE3B 0
R/W

R/W Start Frame Initiation Request Select
Selects the condition of a start frame initiation
request when a host interrupt request is cleared in
quiet mode.
0: Start frame initiation is requested when all interrupt
requests are cleared
1: Start frame initiation is requested when one or
more interrupt requests are cleared

R/W Interrupt Enable Direct Mode
Specifies whether LPC channel 2 and channel 3
SERIRQ interrupt source (SMI, IRQ6, IRQ9 to
IRQ11) generation is conditional upon OBF, or is
controlled only by the host interrupt enable bit.
0: Host interrupt is requested when host interrupt
enable and corresponding OBF bits are both set to
1
1: Host interrupt is requested when host interrupt
enable bit is set to 1

R/W Host SMI Interrupt Enable 3B
Enables or disables an SMI interrupt request when
OBF3B is set by a TWR15 write.
0: Host SMI interrupt request by OBF3B and
SMIE3B is disabled
[Clearing conditions]
•
Writing 0 to SMIE3B
•
LPC hardware reset, LPC software reset
•
Clearing OBF3B to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
Host SMI interrupt request by setting OBF3B to 1
is enabled
[When IEDIR3 = 1]
Host SMI interrupt is requested
[Setting condition]
•
Writing 1 after reading SMIE3B = 0
Section 18 LPC Interface (LPC)
Rev. 3.00 Jul. 14, 2005 Page 641 of 986
REJ09B0098-0300