Register Descriptions - Renesas H8S Series Hardware Manual

Name Abbreviation
LPC Encoded LDRQ
DMA request
Docking LPC DLDRQ
Encoded DMA
request
Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control input/output
function.
2. Only 0 can be output. If 1 is output, the pin is in the high-impedance state, so an
external resistor is necessary to pull the signal up to VCC.
3. This function becomes available by setting 1 to LPCS in PTCNT2 and one of LPC3E to
LPC1E in HICR0 and LPC4E in HICR4. For details, see section 8.17.3, Port Control
Register 2 (PTCNT2).
4. This function becomes available by setting 1 to LDRQS in PTCNT2 and one of LPC3E
to LPC1E in HICR0 and LPC4E in HICR4. For details, see section 8.17.3, Port Control
Register 2 (PTCNT2).
18.3

Register Descriptions

The LPC has the following registers.
• Host interface control registers 0 to 4 (HICR0 to HICR4)
• LPC channel 3 address registers H and L (LADR3H, LADR3L)
• LPC channel 4 address registers H and L (LADR4H, LADR4L)
• Input data registers 1 to 4 (IDR1 to IDR4)
• Output data registers 1 to 4 (ODR1 to ODR4)
• Bidirectional data registers 0 to 15 (TWR0 to TWR15)
• Status registers 1 to 4 (STR1 to STR4)
• SERIRQ control registers 0 to 2 (SIRQCR0 to SIRQCR2)
• Host interface select register (HISEL)
The following registers are needed to use LPC/FW memory cycles.
• RAM buffer address register (RBUFAR)
• Flash memory programming address registers H and L (FLWARH, FLWARL)
• Manufacture and device ID code registers (LMCMIDCR, LMCDIDCR)
• Erase block register (EBLKR)
• LMC status registers 1 and 2 (LMCST1, LMCST2)
• LMC control registers 1 and 2 (LMCCR1, LMCCR2)
Port I/O
4
PC6 Output*
4
PC7 Input*
Section 18 LPC Interface (LPC)
Function
DMA request signal
DMA request signal
Rev. 3.00 Jul. 14, 2005 Page 617 of 986
REJ09B0098-0300