On-Chip Ram Host Base Address Registers H And L; (Rambarh And Rambarl) - Renesas H8S Series Hardware Manual

18.3.22 On-Chip RAM Host Base Address Registers H and L (RAMBARH and
RAMBARL)
RAMBAR stores the upper 16 bits of the host start address when a host address is translated into
an on-chip RAM address. The lower 16 bits of the host start address are fixed H'0000. The host
address space to be translated is decided in combination with the RAMASSR contents which
select the size of the host address space. When the FW memory cycle is used, bits 7 to 4 in
RABAHR (MRA31 to MRA28) are used as IDSEL. The contents of this register must not be
changed in LPC/FW memory cycles (while LMCE is set to 1).
The host address space of which lower 16 bits are H'FFF0 to H'FFFF is used as command space.
• RAMBARH
Bit Bit Name Initial Value Slave Host Description
7 MRA31 0
6 MRA30 0
5 MRA29 0
4 MRA28 0
3 MRA27 0
2 MRA26 0
1 MRA25 0
0 MRA24 0
• RAMBARL
Bit Bit Name Initial Value Slave Host Description
7 MRA23 0
6 MRA22 0
5 MRA22 0
4 MRA20 0
3 MRA19 0
2 MRA18 0
1 MRA17 0
0 RA16 0
R/W

R/W On-Chip RAM Host Base Address Bits 31 to 24

R/W Store the host base address 31 to 24.

R/W

R/W

R/W

R/W

R/W

R/W
R/W

R/W On-Chip RAM Host Base Address Bits 23 to 16

R/W Store the host base address 23 to 16.

R/W

R/W

R/W

R/W

R/W
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R/W
Section 18 LPC Interface (LPC)
Rev. 3.00 Jul. 14, 2005 Page 667 of 986
REJ09B0098-0300