Number Of Dtc Execution States; Table 7.6 Dtc Execution Status; Table 7.7 Number Of States Required For Each Execution Status - Renesas H8S Series Hardware Manual

Section 7 Data Transfer Controller (DTC)
7.5.7

Number of DTC Execution States

Table 7.6 lists the execution status for a single DTC data transfer, and table 7.7 shows the number
of states required for each execution status.
Table 7.6 DTC Execution Status
Vector Read
Mode I
Normal 1
Repeat 1
Block transfer 1
[Legend]
N: Block size (initial setting of CRAH and CRAL)
Table 7.7 Number of States Required for Each Execution Status
Object to be Accessed
Bus width
Access states
Execution Vector read S
status
Register
information
read/write
Byte data read
Word data read
Byte data write
Word data write
Internal operation
Rev. 3.00 Jul. 14, 2005 Page 154 of 986
REJ09B0098-0300
Register
Information
Read/Write
J
6
6
6
On-Chip RAM
(H'(FF)EC00 to
H'(FF)EFFF)
32
1
—
I
1
S
J
1
S
K
1
S
K
1
S
L
1
S
L
1
S
M
Data Read
K
1
1
N
On-Chip RAM
(On-chip RAM area
other than H'(FF)EC00
to H'(FF)EFFF)
16
1
—
—
1
1
1
1
1
Internal
Data Write Operations
L M
1 3
1 3
N 3
On-
Chip On-Chip I/O
ROM Registers
16 8
1 2
1 —
— —
1 2
1 4
1 2
1 4
1 1
16
2
—
—
2
2
2
2
1