Host Base Address Registers 1H And 1L (Hbar1H And Hbar1L) - Renesas H8S Series Hardware Manual

18.3.20 Host Base Address Registers 1H and 1L (HBAR1H and HBAR1L)

HBAR1 stores the upper 16 bits of a host start address when a host address is translated into a
flash memory address. The inverted signal level of pin LID3 is reflected in the MSB of HBAR1.
The lower 16 bits of the host start address are fixed H'0000. The host address space to be
translated is decided in combination with bits AS13 to AS10 in ASSR which select the size of the
host address space. When the FW memory cycle is used, bits 7 to 4 in HBAR1H (HB1A31 to
HB1A28) are used as IDSEL. The contents of this register must not be changed in LPC/FW
memory cycles (while LMCE is set to 1).
• HBAR1H
Bit Bit Name Initial Value Slave Host Description

7 HB1A31
6 HB1A30 0
5 HB1A29 0
4 HB1A28 0
3 HB1A27 0
2 HB1A26 0
1 HB1A25 0
0 HB1A24 0
• HBAR1L
Bit Bit Name Initial Value Slave Host Description
7 HB1A23 0
6 HB1A22 0
5 HB1A22 0
4 HB1A20 0
3 HB1A19 0
2 HB1A18 0
1 HB1A17 0
0 HB1A16 0
R/W

R Host Base Address Bits 31 to 24

R/W Store the host base address 31 to 24. Bit HB1A31
reflects the inverted signal level of pin LID3.

R/W

R/W

R/W

R/W

R/W

R/W
R/W

R/W Host Base Address Bits 23 to 16

R/W Store the host base address 23 to 16.

R/W

R/W

R/W

R/W

R/W

R/W
Section 18 LPC Interface (LPC)
Rev. 3.00 Jul. 14, 2005 Page 665 of 986
REJ09B0098-0300