Conflict Between Tgr Write And Compare Match; Figure 12.46 Conflict Between Tcnt Write And Increment Operations; Figure 12.47 Conflict Between Tgr Write And Compare Match - Renesas H8S Series Hardware Manual

Section 12 16-Bit Timer Pulse Unit (TPU)
φ
Address
Write signal
TCNT input
clock
TCNT

Figure 12.46 Conflict between TCNT Write and Increment Operations

12.8.5

Conflict between TGR Write and Compare Match

If a compare match occurs in the T
and the compare match signal is inhibited. A compare match does not occur even if the same value
as before is written. Figure 12.47 shows the timing in this case.
φ
Address
Write signal
Compare
match signal
TCNT
TGR

Figure 12.47 Conflict between TGR Write and Compare Match

Rev. 3.00 Jul. 14, 2005 Page 370 of 986
REJ09B0098-0300
TCNT write cycle
T1 T2
TCNT address
N
TCNT write data
state of a TGR write cycle, the TGR write takes precedence
2
TGR write cycle
T1 T2
TGR address
N
N
TGR write data
M
Prohibited
N+1
M