Renesas H8S Series Hardware Manual page 26

18.4.17 Flash Memory Erasing.......................................................................................... 709
18.5 Interrupt Sources................................................................................................................ 710
18.5.1 IBFI1, IBFI2, IBFI3, IBFI4, LMC, LMCUI, and ERRI ....................................... 710
18.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12 ........................ 711
18.6 Usage Note......................................................................................................................... 714
18.6.1 Data Conflict......................................................................................................... 714
18.6.2 Module Stop Mode Setting ................................................................................... 715
18.6.3 Operating Mode in LPC/FW Memory Write Cycle.............................................. 715
Section 19 A/D Converter ................................................................................. 717
19.1 Features.............................................................................................................................. 717
19.2 Input/Output Pins............................................................................................................... 719
19.3 Register Descriptions......................................................................................................... 720
19.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 720
19.3.2 A/D Control/Status Register (ADCSR) ................................................................ 721
19.3.3 A/D Control Register (ADCR) ............................................................................. 722
19.4 Operation ........................................................................................................................... 723
19.4.1 Single Mode.......................................................................................................... 723
19.4.2 Scan Mode ............................................................................................................ 723
19.4.3 Input Sampling and A/D Conversion Time .......................................................... 724
19.4.4 External Trigger Input Timing.............................................................................. 726
19.5 Interrupt Source ................................................................................................................. 727
19.6 A/D Conversion Accuracy Definitions .............................................................................. 727
19.7 Usage Notes ....................................................................................................................... 729
19.7.1 Permissible Signal Source Impedance .................................................................. 729
19.7.2 Influences on Absolute Accuracy ......................................................................... 729
19.7.3 Setting Range of Analog Power Supply and Other Pins....................................... 730
19.7.4 Notes on Board Design ......................................................................................... 730
19.7.5 Notes on Noise Countermeasures ......................................................................... 730
19.7.6 Module Stop Mode Setting ................................................................................... 731
Section 20 RAM ................................................................................................ 733
Section 21 Flash Memory (0.18-µm F-ZTAT Version).................................... 735
21.1 Features.............................................................................................................................. 735
21.1.1 Mode Transitions .................................................................................................. 737
21.1.2 Mode Comparison ................................................................................................ 738
21.1.3 Flash Memory MAT Configuration...................................................................... 739
21.1.4 Block Division ...................................................................................................... 739
21.1.5 Programming/Erasing Interface ............................................................................ 742
Rev. 3.00 Jul. 14, 2005 Page xxvi of xlviii