Serial Timer Control Register (Stcr) - Renesas H8S Series Hardware Manual

3.2.3

Serial Timer Control Register (STCR)

STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.
Bit Bit Name Initial Value
7 IICS 0
6 IICX1 0
5 IICX0 0
R/W Description
2
R/W I C Extra Buffer Select
Sets bits 7 to 4 of port A to form an output buffer similar
to SCL and SDA. This function is used to realize the I
interface only by software.
0: PA7 to PA4 are normal I/O pins
1: PA7 to PA4 are I/O pins that can be bus driven
2
R/W I C Transfer Rate Select 1, 0
R/W
These bits control the IIC operation. These bits select
the transfer rate in master mode together with bits
CKS2 to CKS0 in the I
details on the transfer rate, see table 16.3.
Section 3 MCU Operating Modes
2
C bus mode register (ICMR). For
Rev. 3.00 Jul. 14, 2005 Page 63 of 986
REJ09B0098-0300
2
C