Pwmx (D/A) Data Registers A And B (Dadra And Dadrb) - Renesas H8S Series Hardware Manual

Section 10 14-Bit PWM Timer (PWMX)
10.3.2

PWMX (D/A) Data Registers A and B (DADRA and DADRB)

DADRA corresponds to PWMX (D/A) channel A, and DADRB to PWMX (D/A) channel B. As
DACNT is 16 bits, data transfer between the CPU is performed through the temporary register
(TEMP). For details, see section 10.4, Bus Master Interface.
• DADRA
Bit Bit Name Initial Value
15 DA13 1
14 DA12 1
13 DA11 1
12 DA10 1
11 DA9 1
10 DA8 1
9 DA7 1
8 DA6 1
7 DA5 1
6 DA4 1
5 DA3 1
4 DA2 1
3 DA1 1
2 DA0 1
1 CFS 1

0 1
Rev. 3.00 Jul. 14, 2005 Page 262 of 986
REJ09B0098-0300
R/W Description
R/W D/A Data 13 to 0
R/W These bits set a digital value to be converted to an
analog value.
R/W
In each base cycle, the DACNT value is continually
R/W
compared with the DADR value to determine the duty
R/W
cycle of the output waveform, and to decide whether to
output a fine-adjustment pulse equal in width to the
R/W
resolution. To enable this operation, this register must
R/W
be set within a range that depends on the CFS bit. If
R/W
the DADR value is outside this range, the PWM output
is held constant.
R/W
A channel can be operated with 12-bit precision by
R/W
fixing DA0 and DA1 to 0. The two data bits are not
R/W
compared with DACNT12 and DACNT13 of DACNT.
R/W
R/W
R/W
R/W Carrier Frequency Select
0: Base cycle = resolution (T) × 64
The range of DA13 to DA0: H'0100 to H'3FFF
1: Base cycle = resolution (T) × 256
The range of DA13 to DA0: H'0040 to H'3FFF
R Reserved
Always read as 1 and cannot be modified.