Renesas H8S Series Hardware Manual page 674

Section 18 LPC Interface (LPC)
Bit Bit Name Initial Value Slave Host Description
5 SDWN 0
4 ABRT 0
Rev. 3.00 Jul. 14, 2005 Page 626 of 986
REJ09B0098-0300
R/W
R/(W)* 
LPC Shutdown Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when an LPC hardware shutdown request is
generated.
0: [Clearing conditions]
•
Writing 0 after reading SDWN = 1
•
LPC hardware reset
(LRESET pin falling edge detection)
•
LPC software reset (LRSTB = 1)
1: [Setting condition]
LPCPD pin falling edge detection
•
R/(W)* 
LPC Abort Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when a forced termination (abort) of an LPC transfer
cycle occurs.
0: [Clearing conditions]
•
Writing 0 after reading ABRT = 1
•
LPC hardware reset
(LRESET pin falling edge detection)
•
LPC software reset (LRSTB = 1)
•
LPC hardware shutdown
(SDWNE = 1 and LPCPD pin falling edge
detection)
•
LPC software shutdown (SDWNB = 1)
1: [Setting condition]
LFRAME pin falling edge detection during LPC
•
transfer cycle