Section 18 LPC Interface (LPC)
Bit
Bit Name Initial Value Slave Host Description
0
IRQ6E2
0
Rev. 3.00 Jul. 14, 2005 Page 648 of 986
REJ09B0098-0300
R/W
R/W
Host IRQ6 Interrupt Enable 3
Enables or disables an HIRQ6 interrupt request
when OBF2 is set by an oDR2 write.
0: HIRQ6 interrupt request by OBF2 and IRQE6E2
is disabled
[Clearing conditions]
•
Writing 0 to IRQ6E2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR2 = 0)
1: [When IEDIR2 = 0]
HIRQ6 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR2 = 1]
HIRQ6 interrupt is requested
[Setting condition]
•
Writing 1 after reading IRQ6E2 = 0