Renesas H8S Series Hardware Manual page 491

Bit Bit Name
2 TEND
1 MPB
0 MPBT
Notes: 1. Only 0 can be written to clear the flag.
2. etu: Element Time Unit (time taken to transfer one bit)
Initial Value R/W
1 R
0 R
0 R/W
Section 15 Serial Communication Interface (SCI, IrDA)
Description
Transmit End
TEND is set to 1 when the receiving end
acknowledges no error signal and the next
transmit data is ready to be transferred to TDR.
[Setting conditions]
•
When both TE and EPS in SCR are 0
•
When ERS = 0 and TDRE = 1 after a specified
time passed after the start of 1-byte data
transfer. The set timing depends on the
register setting as follows.
•
When GM = 0 and BLK = 0, 2.5 etu*
transmission start
•
When GM = 0 and BLK = 1, 1.5 etu*
transmission start
•
When GM = 1 and BLK = 0, 1.0 etu*
transmission start
•
When GM = 1 and BLK = 1, 1.0 etu*
transmission start
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE
= 1
•
When a TXI interrupt request is issued
allowing DTC to write the next data to TDR
Multiprocessor Bit
Not used in smart card interface mode.
Multiprocessor Bit Transfer
Write 0 to this bit in smart card interface mode.
Rev. 3.00 Jul. 14, 2005 Page 443 of 986
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REJ09B0098-0300