Renesas H8S Series Hardware Manual page 37

Figure 15.40 Switching from SCK Pins to Port Pins.................................................................. 503
Figure 15.41 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins.......... 504
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Section 16 I C Bus Interface (IIC)
Figure 16.1 Block Diagram of I
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Figure 16.2 I C Bus Interface Connections (Example: This LSI as Master) .............................. 508
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Figure 16.3 I C Bus Data Format (I
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Figure 16.4 I C Bus Data Format (Serial Format) ...................................................................... 535
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Figure 16.5 I C Bus Timing........................................................................................................ 536
Figure 16.6 Sample Flowchart for IIC Initialization................................................................... 537
Figure 16.7 Sample Flowchart for Operations in Master Transmit Mode .................................. 538
Figure 16.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0)....... 540
Figure 16.9 Example of Stop Condition Issuance Operation Timing in Master Transmit Mode
(MLS = WAIT = 0) ................................................................................................. 541
Figure 16.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1) ............. 542
Figure 16.11 Example of Operation Timing in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1) ............................................................................ 544
Figure 16.12 Example of Stop Condition Issuance Operation Timing in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1) ............................................................................ 544
Figure 16.13 Sample Flowchart for Operations in Master Receive Mode
(receiving multiple bytes) (WAIT = 1).................................................................. 546
Figure 16.14 Sample Flowchart for Operations in Master Receive Mode
(receiving a single byte) (WAIT = 1) .................................................................... 547
Figure 16.15 Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1) ............................................................................ 550
Figure 16.16 Example of Stop Condition Issuance Timing in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1) ............................................................................ 550
Figure 16.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1) ............... 552
Figure 16.18 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS= 1) ... 554
Figure 16.19 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS= 1) ... 555
Figure 16.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) ............... 556
Figure 16.21 Example of Slave Receive Mode Operation Timing (1)
(MLS = ACKB = 0, HNDS = 0)............................................................................ 558
Figure 16.22 Example of Slave Receive Mode Operation Timing (2)
(MLS = ACKB = 0, HNDS = 0)............................................................................ 558
Figure 16.23 Sample Flowchart for Slave Transmit Mode......................................................... 559
Figure 16.24 Example of Slave Transmit Mode Operation Timing (MLS = 0) ......................... 561
Figure 16.25 IRIC Setting Timing and SCL Control (1) ............................................................ 562
Figure 16.26 IRIC Setting Timing and SCL Control (2) ............................................................ 563
Figure 16.27 IRIC Setting Timing and SCL Control (3) ............................................................ 564
Figure 16.28 Block Diagram of Noise Canceller........................................................................ 567
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C Bus Interface........................................................................ 507
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C Bus Format)................................................................... 535
Rev. 3.00 Jul. 14, 2005 Page xxxvii of xlviii