Section 5 Interrupt Controller; Features - Renesas H8S Series Hardware Manual

5.1

Features

• Two interrupt control modes
Two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system
control register (SYSCR).
• Priorities settable with ICR
An interrupt control register (ICR) is provided for setting in each module interrupt priority
levels for all interrupt requests excluding NMI and address breaks.
• Three-level interrupt mask control
By means of the interrupt control mode, I and UI bits in CCR and ICR, 3-level interrupt mask
control is performed.
• Independent vector addresses
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
• Forty-nine external interrupt pins
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level
sensing, can be independently selected for IRQ15 to IRQ0. When the EIVS bit in the system
control register 3 (SYSCR3) is cleared to 0, the IRQ6 interrupt is generated by IRQ6 or KIN7
to KIN0. The IRQ7 interrupt is generated by IRQ7, KIN15 to KIN8, or WUE7 to WUE0.
When the EIVS bit in the system control register 3 (SYSCR3) is set to 1, an interrupt is
requested at the falling edge of KIN15 to KIN0 and WUE15 to WUE0.
• DTC control
The DTC can be activated by an interrupt request.
• Two interrupt vector addresses are selectable
H8S/2140B Group compatible interrupt vector addresses or extended interrupt vector
addresses are selected depending on the EIVS bit in system control register 3 (SYSCR3). In
extended mode, independent vector addresses are assigned for the interrupt vector addresses of
KIN7 to KIN0, KIN15 to KIN8, and WUE7 to WUE0 interrupts.
• General ports for IRQ15 to IRQ0 input are selectable

Section 5 Interrupt Controller

Section 5 Interrupt Controller

Rev. 3.00 Jul. 14, 2005 Page 79 of 986
REJ09B0098-0300