Conflict Between Timer Counter (Tcnt) Write And Increment; Figure 14.7 Conflict Between Tcnt Write And Increment - Renesas H8S Series Hardware Manual

(2) Reading from TCNT and TCSR (Example of WDT_0)
These registers are read in the same way as other registers. The read address is H'FFA8 for TCSR
and H'FFA9 for TCNT.
14.6.2

Conflict between Timer Counter (TCNT) Write and Increment

If a timer counter clock pulse is generated during the T
takes priority and the timer counter is not incremented. Figure 14.7 shows this operation.
φ
Address
Internal write signal
TCNT input clock
TCNT

Figure 14.7 Conflict between TCNT Write and Increment

state of a TCNT write cycle, the write
2
TCNT write cycle
T 1 T 2
N
Counter write data
Rev. 3.00 Jul. 14, 2005 Page 425 of 986
Section 14 Watchdog Timer (WDT)
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REJ09B0098-0300