Conflict Between Buffer Register Write And Compare Match; Figure 12.48 Conflict Between Buffer Register Write And Compare Match - Renesas H8S Series Hardware Manual

12.8.6

Conflict between Buffer Register Write and Compare Match

If a compare match occurs in the T
buffer operation will be the data prior to the write. Figure 12.48 shows the timing in this case.
φ
Address
Write signal
Compare
match signal
Buffer
register
TGR

Figure 12.48 Conflict between Buffer Register Write and Compare Match

state of a TGR write cycle, the data transferred to TGR by the
2
TGR write cycle
T1 T2
Buffer register
address
N
Section 12 16-Bit Timer Pulse Unit (TPU)
Buffer register write data
M
N
Rev. 3.00 Jul. 14, 2005 Page 371 of 986
REJ09B0098-0300