Watch Mode - Renesas H8S Series Hardware Manual
16-bit single-chip microcomputer
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Also See for H8S Series:
- Hardware manual (1047 pages) ,
- User manual (38 pages) ,
- Hardware manual (875 pages)
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Section 24 Power-Down Modes
24.7
Watch Mode
The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed
mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR
cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1.
In watch mode, the CPU is stopped and on-chip peripheral modules other than WDT_1 are also
stopped. The contents of the CPU's internal registers, several on-chip peripheral module registers,
and on-chip RAM data are retained and the I/O ports retain their values before transition as long
as the prescribed voltage is supplied.
Watch mode is cleared by an interrupt (WOVI1, NMI, IRQ0 to IRQ15, KIN0 to KIN15, or
WUE0 to WUE15), KBU interrupt, RES pin input, or STBY pin input.
When an interrupt occurs, watch mode is cleared and a transition is made to high-speed mode or
medium-speed mode when the LSON bit in LPWRCR cleared to 0, or a transition is made to
subactive mode when the LSON bit is set to 1. When a transition is made to high-speed mode, a
stable clock is supplied to the entire LSI and interrupt exception handling starts after the time set
in the STS2 to STS0 bits in SBYCR has elapsed. In the case of an IRQ0 to IRQ15 interrupt, watch
mode is not cleared if the corresponding enable bit has been cleared to 0 or the interrupt has been
masked by the CPU. In the case of a KIN0 to KIN15 or WUE0 to WUE15 interrupt, watch mode
is not cleared if the input is disabled or the interrupt has been masked by the CPU. In the case of
an interrupt from an on-chip peripheral module, watch mode is not cleared if the interrupt enable
register has been set to disable the reception of that interrupt or the interrupt has been masked by
the CPU.
When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with
the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the
RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after
the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Rev. 3.00 Jul. 14, 2005 Page 875 of 986
REJ09B0098-0300
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