Port 5; Port 5 Data Direction Register (P5Ddr); Port 5 Data Register (P5Dr) - Renesas H8S Series Hardware Manual

Section 8 I/O Ports
8.5

Port 5

Port 5 is a 3-bit I/O port. Port 5 pins also function as interrupt input pins, IIC_0 input/output pin,
TMR_Y output pin, and the external sub-clock input pin. The output format for P52 is NMOS
push-pull output. Port 5 has the following registers.

• Port 5 data direction register (P5DDR)

• Port 5 data register (P5DR)

8.5.1 Port 5 Data Direction Register (P5DDR)
The individual bits of P5DDR specify input or output for the pins of port 5.
Bit Bit Name
7 to 3 
2 P52DDR
1 P51DDR
0 P50DDR
8.5.2 Port 5 Data Register (P5DR)
P5DR stores output data for the port 5 pins.
Bit Bit Name
7 to 3 
2 P52DR
1 P51DR
0 P50DR
Rev. 3.00 Jul. 14, 2005 Page 178 of 986
REJ09B0098-0300
Initial Value R/W

Undefined
0 W
0 W
0 W
Initial Value R/W

All 1
0 R/W
0 R/W
0 R/W
Description
Reserved
These bits cannot be modified.
If port 5 pins are specified for use as the general I/O
port, the corresponding port 5 pins are output ports
when the P5DDR bits are set to 1, and input ports
when cleared to 0.
Description
Reserved
These bits are always read as 1 and cannot be
modified.
P5DR stores output data for the port 5 pins that are
used as the general output port.
If a port 5 read is performed while the P5DDR bits
are set to 1, the P5DR values are read. If a port 5
read is performed while the P5DDR bits are cleared
to 0, the pin states are read.