Table 13.2 Clock Input To Tcnt And Count Condition (1) - Renesas H8S Series Hardware Manual

Section 13 8-Bit Timer (TMR)

Table 13.2 Clock Input to TCNT and Count Condition (1)

Channel CKS2
CKS1
TMR_0 0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
TMR_1 0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
Rev. 3.00 Jul. 14, 2005 Page 386 of 986
REJ09B0098-0300
TCR
CKS0 ICKS1
0 —
1 —
1 —
0 —
0 —
1 —
1 —
0 —
0 —
1 0
1 1
0 0
0 1
1 0
1 1
0 —
STCR
Description
ICKS0
— Disables clock input
0 Increments at falling edge of internal
clock φ/8
1 Increments at falling edge of internal
clock φ/2
0 Increments at falling edge of internal
clock φ/64
1 Increments at falling edge of internal
clock φ/32
0 Increments at falling edge of internal
clock φ/1024
1 Increments at falling edge of internal
clock φ/256
— Increments at overflow signal from
TCNT_1*
— Disables clock input
— Increments at falling edge of internal
clock φ/8
— Increments at falling edge of internal
clock φ/2
— Increments at falling edge of internal
clock φ/64
— Increments at falling edge of internal
clock φ/128
— Increments at falling edge of internal
clock φ/1024
— Increments at falling edge of internal
clock φ/2048
— Increments at compare-match A from
TCNT_0*