Multiprocessor Serial Data Transmission; Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart - Renesas H8S Series Hardware Manual

Section 15 Serial Communication Interface (SCI, IrDA)
15.5.1

Multiprocessor Serial Data Transmission

Figure 15.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
Start transmission
Read TDRE flag in SSR
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
All data transmitted?
Read TEND flag in SSR
Break output?
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0

Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart

Rev. 3.00 Jul. 14, 2005 Page 468 of 986
REJ09B0098-0300
Initialization
No
TDRE = 1
Yes
No
Yes
No
TEND = 1
Yes
No
Yes
<End>
[1] SCI initialization:
[1]
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
frame of 1s is output, and
[2]
transmission is enabled.
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
[3]
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to 0.
However, the TDRE flag is
checked and cleared
automatically when the DTC is
initiated by a transmit data empty
interrupt (TXI) request and writes
data to TDR.
[4] Break output at the end of serial
[4]
transmission:
To output a break in serial
transmission, set port DDR to 1,
clear DR to 0, and then clear the
TE bit in SCR to 0.