Renesas H8S Series Hardware Manual page 38

Figure 16.29 Notes on Reading Master Receive Data ................................................................ 573
Figure 16.30 Flowchart for Start Condition Issuance Instruction for Retransmission and
Timing................................................................................................................... 574
Figure 16.31 Stop Condition Issuance Timing ........................................................................... 575
Figure 16.32 IRIC Flag Clearing Timing when WAIT = 1 ........................................................ 576
Figure 16.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode........................... 577
Figure 16.34 TRS Bit Set Timing in Slave Mode....................................................................... 578
Figure 16.35 Diagram of Erroneous Operation when Arbitration is Lost .................................. 580
Section 17 Keyboard Buffer Control Unit (KBU)
Figure 17.1 Block Diagram of KBU........................................................................................... 582
Figure 17.2 KBU Connection ..................................................................................................... 583
Figure 17.3 Sample Receive Processing Flowchart.................................................................... 594
Figure 17.4 Receive Timing ....................................................................................................... 595
Figure 17.5 Sample Transmit Processing Flowchart .................................................................. 596
Figure 17.6 Transmit Timing...................................................................................................... 597
Figure 17.7 (1) Sample Receive Abort Processing Flowchart.................................................... 598
Figure 17.7 (2) Sample Receive Abort Processing Flowchart.................................................... 599
Figure 17.8 Receive Abort and Transmit Start (Transmission/Reception Switchover)
Timing..................................................................................................................... 599
Figure 17.9 KCLKI and KDI Read Timing ................................................................................ 600
Figure 17.10 KCLKO and KDO Write Timing .......................................................................... 601
Figure 17.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing ..................... 602
Figure 17.12 Receive Counter and KBBR Data Load Timing ................................................... 603
Figure 17.13 Receive Timing and KCLK................................................................................... 604
Figure 17.14 Example of KCLK Input Fall Interrupt Operation ................................................ 605
Figure 17.15 Timing of First KCLK Interrupt............................................................................ 606
Figure 17.16 First KCLK Interrupt Path..................................................................................... 608
Figure 17.17 Interrupt Timing in Software Standby Mode, Watch Mode, and Subsleep Mode. 609
Figure 17.18 Internal Flag of First KCLK Falling Interrupt in Software Standby mode,
Watch mode, and Subsleep mode.......................................................................... 610
Figure 17.19 KBIOE Setting and KCLK Falling Edge Detection Timing ................................. 611
Figure 17.20 KDO Output .......................................................................................................... 612
Section 18 LPC Interface (LPC)
Figure 18.1 Block Diagram of LPC............................................................................................ 615
Figure 18.2 Typical LFRAME Timing....................................................................................... 679
Figure 18.3 Abort Mechanism.................................................................................................... 679
Figure 18.4 GA20 Output........................................................................................................... 681
Figure 18.5 Power-Down State Termination Timing ................................................................. 686
Figure 18.6 SERIRQ Timing...................................................................................................... 687
Rev. 3.00 Jul. 14, 2005 Page xxxviii of xlviii