Noise Cancel Cycle Setting Register - Renesas H8S Series Hardware Manual

Section 8 I/O Ports
8.16.6 Noise Cancel Cycle Setting Register (PGNCCS)
PGNCCS controls the sampling cycles of the noise canceller.
Bit Bit Name
7 to 3 
2 PGNCCK2
1 PGNCCK1
0 PGNCCK0
Rev. 3.00 Jul. 14, 2005 Page 236 of 986
REJ09B0098-0300
Initial Value R/W
Undefined R/W
0 R/W
0 R/W
0 R/W
Description
Reserved
The read data is undefined. The initial value should
not be changed.
These bits set the sampling cycles of the noise
canceller.
When φ is 10 MHz
0.88 µs
000:
12.8 µs
001:
010: 3.3 ms
011: 6.6 ms
100: 13.1 ms
101: 26.2 ms
110: 52.4 ms
111: 104.9 ms
φ/2
φ/32
φ/8192
φ/16384
φ/32768
φ/65536
φ/131072
φ/262144