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Section 10 16-Bit Timer Pulse Unit (TPU)
φ
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register
Figure 10.50 Conflict between Buffer Register Write and Input Capture
10.8.10 Conflict between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence. Figure 10.51 shows the operation timing when a
TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
Figure 10.51 Conflict between Overflow and Counter Clearing
Rev. 1.00 Apr. 28, 2008 Page 302 of 994
REJ09B0452-0100
Buffer register write cycle
φ
TCNT input
clock
TCNT
H'FFFF
Counter
clear signal
TGF
Disabled
TCFV
T1
T2
Buffer register
address
N
M
N
M
H'0000
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