Overflow Flags In Reset Synchronous Pwm Mode; Contention Between Overflow/Underflow And Counter Clearing - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.7.16

Overflow Flags in Reset Synchronous PWM Mode

When set to reset synchronous PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of TSTR is set to 1.
At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting.
In reset synchronous PWM mode, with cycle register TGRA_3's set value at H'FFFF, when specifying TGR3A compare-
match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF, then a compare-match occurs with
TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this point, TSR's overflow flag TCFV bit is not set.
Figure 10.110 shows a TCFV bit operation example in reset synchronous PWM mode with a set value for cycle register
TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without synchronous setting for the counter
clear source.
TGRA_3
(H'FFFF)
H'0000
TCFV_3
TCFV_4
Figure 10.110 Reset Synchronous PWM Mode Overflow Flag
10.7.17

Contention between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT
clearing takes precedence.
Figure 10.111 shows the operation timing when a TGR compare match is specified as the clearing source, and when
H'FFFF is set in TGR.
Figure 10.111 Contention between Overflow and Counter Clearing
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Counter cleared by compare match 3A
TCNT_3 = TCNT_4
P0φ
TCNT input
clock
TCNT
H'FFFF
Counter clear
signal
TGF
Disabled
TCFV
10. Multi-Function Timer Pulse Unit 2
Not set
Not set
H'0000
10-150