Noise Cancel Cycle Setting Register (Pcnccs); Pin Functions - Renesas H8S Series Hardware Manual

Section 8 I/O Ports
8.12.6

Noise Cancel Cycle Setting Register (PCNCCS)

PCNCCS controls the sampling cycles of the noise canceller.
Bit Bit Name
7 to 3 
2 PCNCCK2
1 PCNCCK1
0 PCNCCK0
8.12.7

Pin Functions

• PC7/WUE15/DLDRQ
The pin function is switched as shown below according to the combination of the LDRQS bit
in PTCNT2 and the PC7DDR. When the WUEMR15 bit in WUEMR of the interrupt
controller is cleared to 0, this pin can be used as the WUE15 input pin.
LDRQS
PC7DDR
Pin Function
Rev. 3.00 Jul. 14, 2005 Page 212 of 986
REJ09B0098-0300
Initial Value R/W
Undefined R/W
0 R/W
0 R/W
0 R/W
0
PC7 input pin
Description
Reserved
The read data is undefined. The initial value should
not be changed.
These bits set the sampling cycles of the noise
canceller.
When φ is 10 MHz
0.88 µs
000:
12.8 µs
001:
010: 3.3 ms
011: 6.6 ms
100: 13.1 ms
101: 26.2 ms
110: 52.4 ms
111: 104.9 ms
0
1
PC7 output pin
WUE15 input pin
φ/2
φ/32
φ/8192
φ/16384
φ/32768
φ/65536
φ/131072
φ/262144
1

DLDRQ input pin