Conflict Between Tcnt Write And Clear Operations; Conflict Between Tcnt Write And Increment Operations; Figure 12.45 Conflict Between Tcnt Write And Clear Operations - Renesas H8S Series Hardware Manual

12.8.3

Conflict between TCNT Write and Clear Operations

If the counter clear signal is generated in the T
precedence and the TCNT write is not performed. Figure 12.45 shows the timing in this case.
φ
Address
Write signal
Counter clear
signal
TCNT

Figure 12.45 Conflict between TCNT Write and Clear Operations

12.8.4

Conflict between TCNT Write and Increment Operations

If incrementing occurs in the T
and TCNT is not incremented. Figure 12.46 shows the timing in this case.
state of a TCNT write cycle, TCNT clearing takes
2
TCNT write cycle
T1
TCNT address
N
state of a TCNT write cycle, the TCNT write takes precedence
2
Section 12 16-Bit Timer Pulse Unit (TPU)
T2
H'0000
Rev. 3.00 Jul. 14, 2005 Page 369 of 986
REJ09B0098-0300