Page 1 All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp.
Page 2 Rev.2.00 Jun. 28, 2007 Page ii of xxii...
Page 3 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
Page 4 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 5: How To Use This Manual
It does not cover all revised items. For details on the revised points, see the actual locations in the manual. The following documents have been prepared for the H8SX/1650 Group. Before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document.
Page 6 2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name"...
Page 7 3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. [Bit Chart] Bit: ...
Page 8 4. Description of Abbreviations The abbreviations used in this manual are listed below. • Abbreviations specific to this product Abbreviation Description Bus controller Clock pulse generator Data transfer controller INTC Interrupt controller Programmable pulse generator Serial communication interface 8-bit timer 16-bit timer pulse unit Watchdog timer •...
Page 9: Table Of Contents
Contents Section 1 Overview....................1 Features..........................1 1.1.1 Applications ......................1 1.1.2 Overview of Functions..................2 List of Products........................7 Block Diagram........................8 Pin Assignments ........................9 Pin Functions ........................10 Section 2 CPU......................15 Features..........................15 CPU Operating Modes......................17 2.2.1 Normal Mode......................
Page 10 2.8.2 Register Indirect—@ERn................... 51 2.8.3 Register Indirect with Displacement—@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn)...................... 51 2.8.4 Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)....51 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn− ......52 2.8.6 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32........
Page 11 4.5.2 Address Error Exception Handling ..............77 Interrupts..........................78 4.6.1 Interrupt Sources....................78 4.6.2 Interrupt Exception Handling ................78 Instruction Exception Handling ..................79 4.7.1 Trap Instruction Exception Handling..............79 4.7.2 Sleep Instruction Exception Handling ..............80 4.7.3 Exception Handling by Illegal Instruction ............81 Stack Status after Exception Handling................
Page 12 5.8.6 Interrupts Source Flag of Peripheral Modules ..........119 Section 6 Bus Controller (BSC) ................ 121 Features..........................121 Register Descriptions......................124 6.2.1 Bus Width Control Register (ABWCR)............124 6.2.2 Access State Control Register (ASTCR) ............126 6.2.3 Wait Control Registers A and B (WTCRA, WTCRB) ........127 6.2.4 Read Strobe Timing Control Register (RDNCR) ..........
Page 13 6.7.7 Extension of Chip Select (CS) Assertion Period..........185 Burst ROM Interface ......................185 6.8.1 Burst ROM Space Setting................. 185 6.8.2 Data Bus......................186 6.8.3 I/O Pins Used for Burst ROM Interface............186 6.8.4 Basic Timing..................... 187 6.8.5 Wait Control ..................... 189 6.8.6 Read Strobe (RD) Timing.................
Page 14 7.2.1 DTC Mode Register A (MRA) ................. 220 7.2.2 DTC Mode Register B (MRB)................221 7.2.3 DTC Source Address Register (SAR)............... 223 7.2.4 DTC Destination Address Register (DAR)............223 7.2.5 DTC Transfer Count Register A (CRA) ............224 7.2.6 DTC Transfer Count Register B (CRB)............224 7.2.7 DTC Enable Registers A to H (DTCERA to DTCERH) ........
Page 15 8.1.1 Data Direction Register (PnDDR) (n = 1 to 3, 6, A, B, D to F, H, and I) ..258 8.1.2 Data Register (PnDR) (n = 1 to 3, 6, A, B, D to F, H, and I)......259 8.1.3 Port Register (PORTn) (n = 1 to 3, 5, 6, A, B, D to F, H, and I) ......
Page 16 9.3.4 Timer Interrupt Enable Register (TIER)............337 9.3.5 Timer Status Register (TSR)................339 9.3.6 Timer Counter (TCNT)..................343 9.3.7 Timer General Register (TGR) ................. 343 9.3.8 Timer Start Register (TSTR) ................344 9.3.9 Timer Synchronous Register (TSYR)............... 345 Operation .......................... 346 9.4.1 Basic Functions....................
Page 17 10.3.2 Output Data Registers H, L (PODRH, PODRL)..........394 10.3.3 Next Data Registers H, L (NDRH, NDRL) ............395 10.3.4 PPG Output Control Register (PCR) ..............398 10.3.5 PPG Output Mode Register (PMR) ..............399 10.4 Operation .......................... 401 10.4.1 Output Timing....................
Page 18 11.6.2 Compare Match Count Mode................430 11.7 Interrupt Sources....................... 431 11.7.1 Interrupt Sources and DTC Activation ............. 431 11.7.2 A/D Converter Activation................. 431 11.8 Usage Notes ........................432 11.8.1 Notes on Setting Cycle ..................432 11.8.2 Conflict between TCNT Write and Clear ............432 11.8.3 Conflict between TCNT Write and Increment..........
Page 19 13.3.2 Receive Data Register (RDR) ................454 13.3.3 Transmit Data Register (TDR)................454 13.3.4 Transmit Shift Register (TSR) ................455 13.3.5 Serial Mode Register (SMR) ................455 13.3.6 Serial Control Register (SCR)................458 13.3.7 Serial Status Register (SSR) ................463 13.3.8 Smart Card Mode Register (SCMR)..............
Page 20 13.9 Usage Notes ........................519 13.9.1 Module Stop State Setting ................519 13.9.2 Break Detection and Processing ............... 519 13.9.3 Mark State and Break Detection ............... 519 13.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ..............519 13.9.5 Relation between Writing to TDR and TDRE Flag ..........
Page 21 15.5 Usage Notes ........................550 15.5.1 Module Stop State Setting ................550 15.5.2 D/A Output Hold Function in Software Standby Mode........550 Section 16 RAM ....................551 Section 17 Clock Pulse Generator ..............553 17.1 Register Description ......................554 17.1.1 System Clock Control Register (SCKCR) ............554 17.2 Oscillator...........................
Page 22 18.8.4 Timing Sequence at Power-On ................. 581 18.9 Sleep Instruction Exception Handling ................582 18.10 Bφ Clock Output Control....................585 18.11 Usage Notes ........................586 18.11.1 I/O Port Status....................586 18.11.2 Current Consumption during Oscillation Settling Standby Period ....586 18.11.3 DTC Module Stop.....................
Page 23: Section 1 Overview
Section 1 Overview Features The core of each product in the H8SX/1650 Group of CISC (complex instruction set computer) microcomputers is an H8SX CPU, which has an internal 32-bit architecture. The H8SX CPU provides upward-compatibility with the CPUs of other Renesas Technology-original microcomputers;...
Page 24: Overview Of Functions
Section 1 Overview 1.1.2 Overview of Functions Table 1.1 lists the functions of H8SX/1650 Group products in outline. Table 1.1 Overview of Functions Module/ Classification Function Description  • Memory ROM lineup: ROMless versions only • RAM capacity: 24 Kbytes •...
Page 25 Section 1 Overview Module/ Classification Function Description • Interrupt Interrupt Thirteen external interrupt pins (NMI, and IRQ11 to IRQ0) (source) controller • 56 internal interrupt sources (INTC) • Two interrupt control modes (specified by the interrupt control register) • Eight priority orders specifiable (by setting the interrupt priority register) •...
Page 26 Section 1 Overview Module/ Classification Function Description External bus Bus formats extension controller • External memory interfaces (for the connection of ROM, burst (BSC) ROM, SRAM, and byte control SRAM) • Address/data bus format: Support for both separate and multiplexed buses (8-bit access or 16-bit access) •...
Page 27 Section 1 Overview Module/ Classification Function Description • 8-bit resolution × two output channels D/A converter • Output voltage: 0 V to Vref, maximum conversion time: 10 µs converter (DAC) (with 20-pF load) • 8 bits × four channels (can be used as 16 bits × two channels) Timer 8-bit timer •...
Page 28 Section 1 Overview Module/ Classification Function Description • Four channels (select asynchronous or clocked synchronous Serial interface Serial serial communication mode) communi- • cation Full-duplex communication capability • interface Select the desired bit rate and LSB-first or MSB-first transfer (SCI) •...
Page 29: List Of Products
Indicates the product-specific number. H8SX/1650 Group Indicates the type of ROM device. Indicates the product classification Microcomputer R indicates a Renesas semiconductor product. Figure 1.1 How to Read the Product Name Code Rev.2.00 Jun. 28, 2007 Page 7 of 666 REJ09B0311-0200...
Page 30: Block Diagram
Section 1 Overview Block Diagram Port 1 Port 2 Interrupt TMR (unit 0) controller × 2 channels Port 3 TMR (unit 1) × 2 channels Port 5 TPU × 6 channels Port 6 H8SX Port A Port B SCI × 4 channels Port D A/D converter Port E...
Page 31: Pin Assignments
PH3/D3 P65/TMO3 PH2/D2 PH1/D1 P50/AN0/IRQ0-B PH0/D0 P51/AN1/IRQ1-B P52/AN2/IRQ2-B P37/PO15/TIOCA2/TIOCB2/TCLKD-A AVcc P36/PO14/TIOCA2 P53/AN3/IRQ3-B P35/PO13/TIOCA1/TIOCB1/TCLKC-A AVss P34/PO12/TIOCA1 P54/AN4/IRQ4-B P33/PO11/TIOCC0/TIOCD0/TCLKB-A Vref H8SX/1650 Group P32/PO10/TIOCC0/TCLKA-A P55/AN5/IRQ5-B P31/PO9/TIOCA0/TIOCB0 PLQP0120LA-A (FP-120BV) P56/AN6/DA0/IRQ6-B (top view) P57/AN7/DA1/IRQ7-B P30/PO8/TIOCA0 PA0/BREQO/BS-A P27/PO7/TIOCA5/TIOCB5 PA1/BACK/(RD/WR) P26/PO6/TIOCA5/TMO1/TxD1 P25/PO5/TIOCA4/TMCI1/RxD1 PA2/BREQ/WAIT PA3/LLWR/LLB P24/PO4/TIOCA4/TIOCB4/TMRI1/SCK1 PA4/LHWR/LUB P23/PO3/TIOCC3/TIOCD3/IRQ11-A...
Page 32: Pin Functions
Section 1 Overview Pin Functions Table 1.3 Pin Functions Classification Pin Name Description  Power supply Power supply pins. Connect them to the system power supply.  Connect this pin to V via a 0.1-uF capacitor (The capacitor should be placed close to the pin). ...
Page 33 Section 1 Overview Classification Pin Name Description BACK Bus control Output Bus acknowledge signal, which indicates that the bus has been released. BS-A/BS-B Output Indicates the start of a bus cycle. Output Strobe signal which indicates that the output address on the address bus is valid in access to the basic bus interface or byte control SRAM interface space.
Page 34 Section 1 Overview Classification Pin Name Description Interrupt Input Non-maskable interrupt request signal. When this pin is not in use, this signal must be fixed high. IRQ11-A/IRQ11-B Input Maskable interrupt request signal. IRQ10-A/IRQ10-B IRQ9-A/IRQ9-B IRQ8-A/IRQ8-B IRQ7-A/IRQ7-B IRQ6-A/IRQ6-B IRQ5-A/IRQ5-B IRQ4-A/IRQ4-B IRQ3-A/IRQ3-B IRQ2-A/IRQ2-B IRQ1-A/IRQ1-B IRQ0-A/IRQ0-B...
Page 35 Section 1 Overview Classification Pin Name Description 16-bit timer TIOCA2 Input/ Signals for TGRA_2 and TGRB_2. These pins are used as pulse unit (TPU) TIOCB2 output input capture inputs, output compare outputs, or PWM outputs. TIOCA3 Input/ Signals for TGRA_3 to TGRD_3. These pins are used as TIOCB3 output input capture inputs, output compare outputs, or PWM...
Page 36 Section 1 Overview Classification Pin Name Description A/D converter AN7 to AN0 Input Input pins for the analog signals to be processed by the A/D converter. ADTRG0 Input Input pin for the external trigger signal that starts A/D conversion. D/A converter Output Output pins for the analog signals from the D/A converter.
Page 37: Section 2 Cpu
Section 2 CPU Section 2 CPU The H8SX CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16- bit general registers, can handle a 4-Gbyte linear address space, and is ideal for a realtime control system.
Page 38 Transition is made by execution of SLEEP instruction Choice of CPU operating clocks Notes: 1. Advanced mode is only supported as the CPU operating mode of the H8SX/1650 Group. Normal, middle, and maximum modes are not supported. 2. The multiplier and divider are supported by the H8SX/1650 Group.
Page 39: Cpu Operating Modes
Section 2 CPU CPU Operating Modes The H8SX CPU has four operating modes: normal, middle, advanced, and maximum modes. As for selecting the mode, see section 3.1, Operating Mode Selection. Maximum 64 Kbytes for program Normal mode and data areas combined Maximum 16-Mbyte program area and 64-Kbyte data area, Middle mode...
Page 40 Section 2 CPU • Exception Handling Vector Table and Memory Indirect Branch Addresses In normal mode, the top area starting at H'0000 is allocated to the exception handling vector table. One branch address is stored per 16 bits. The structure of the exception handling vector table is shown in figure 2.2.
Page 41: Middle Mode
Section 2 CPU 2.2.2 Middle Mode The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode. • Address Space A maximum address space of 16 Mbytes can be accessed in a total of the program and data areas.
Page 42: Advanced Mode
Section 2 CPU 2.2.3 Advanced Mode The data area in advanced mode is extended to 4 Gbytes as compared with that in middle mode. • Address Space A maximum address space of 4 Gbytes can be linearly accessed. For individual areas, up to 16 Mbytes of the program area and up to 4 Gbytes of the data area can be allocated.
Page 43: Maximum Mode
Section 2 CPU • Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling branch are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. EXR* Reserved Reserved*...
Page 44 Section 2 CPU H'00000000 H'00000001 Reset exception vector H'00000002 H'00000003 H'00000004 Exception vector table H'00000005 H'00000006 H'00000007 Figure 2.6 Exception Handling Vector Table (Maximum Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location.
Page 45: Instruction Fetch
Section 2 CPU Instruction Fetch The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes. It is recommended that the mode should be set according to the bus width of the memory in which the program is stored.
Page 46: Registers
Section 2 CPU Registers The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), 32-bit vector base register (VBR), 32-bit short address base register (SBR), and 64-bit multiply-accumulate register (MAC).
Page 47: General Registers
Section 2 CPU 2.5.1 General Registers The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.
Page 48: Program Counter (Pc)
Section 2 CPU Free area SP (ER7) Stack area Figure 2.11 Stack 2.5.2 Program Counter (PC) PC is a 32-bit counter that indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is two bytes (one word) or a multiple of two bytes, so the least significant PC bit is ignored.
Page 49 Section 2 CPU Initial Bit Name Value Description Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise.
Page 50: Extended Control Register (Exr)
Section 2 CPU 2.5.4 Extended Control Register (EXR) EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0). Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Page 51: Multiply-Accumulate Register (Mac)
Section 2 CPU 2.5.7 Multiply-Accumulate Register (MAC) MAC is a 64-bit register that stores the results of multiply-and-accumulate operations. It consists of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are sign-extended. 2.5.8 Initial Register Values Reset exception handling loads the start address from the vector table into the PC contents, clears...
Page 52: Data Formats
Section 2 CPU Data Formats The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 53: Memory Data Formats
Section 2 CPU 2.6.2 Memory Data Formats Figure 2.13 shows the data formats in memory. The H8SX CPU can access word data and longword data that are stored at any addresses in memory. When word data begin at an odd address or longword data begin at an address other than a multiple of 4, a bus cycle is divided into two or more accesses.
Page 54: Instruction Set
Section 2 CPU Instruction Set The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer B/W/L MOVFPE* , MOVTPE* POP, PUSH* LDM, STM MOVA B/W*...
Page 55 Section 2 CPU Function Instructions Size Types Branch BRA/BS, BRA/BC, BSR/BS, BSR/BC  Bcc* , JMP, BSR, JSR, RTS RTS/L  BRA/S  System control TRAPA, RTE, SLEEP, NOP RTE/L LDC, STC, ANDC, ORC, XORC B/W/L Total [Legend] Byte size Word size Longword size Notes: 1.
Page 56: Instructions And Addressing Modes
Section 2 CPU 2.7.1 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Addressing Mode @(d, @−ERn/ RnL.B/ @ERn+/ Classifi- Rn.W/ @ERn−/ @aa:16/...
Page 57 Section 2 CPU Addressing Mode @(d, @−ERn/ RnL.B/ @ERn+/ Classifi- Rn.W/ @ERn−/ @aa:16/  cation Instruction Size @ERn @(d,ERn) ERn.L) @+ERn @aa:8 @aa:32 Arithmetic MULS, DIVS operations B/W/L EXTU, EXTS   CLRMAC  LDMAC  STMAC Logic AND, OR, XOR B/W/L operations B/W/L...
Page 58 Section 2 CPU Addressing Mode @(d, @−ERn/ RnL.B/ @ERn+/ Classifi- Rn.W/ @ERn−/ @aa:16/  cation Instruction Size @ERn @(d,ERn) ERn.L) @+ERn @aa:8 @aa:32 System B/W* control (CCR, EXR) (VBR, SBR) B/W* (CCR, EXR) (VBR, SBR) ANDC, ORC, XORC  SLEEP ...
Page 59 Section 2 CPU Table 2.2 Combinations of Instructions and Addressing Modes (2) Addressing Mode @(RnL.B/ Rn.W/ Classifi- ERn.L,  cation Instruction Size @ERn @(d,PC) @aa:24 @aa:32 @@aa:8 @@vec:7  Branch BRA/BS, BRA/BC  BSR/BS, BSR/BC    BRA/S  ...
Page 60: Table Of Instructions Classified By Function
Section 2 CPU 2.7.2 Table of Instructions Classified by Function Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in the tables is defined in table 2.3. Table 2.3 Operation Notation Operation Notation Description General register (destination)* General register (source)* General register* General register (32-bit register)
Page 61 Section 2 CPU Table 2.4 Data Transfer Instructions Instruction Size Function #IMM → (EAd), (EAs) → (EAd) B/W/L Transfers data between immediate data, general registers, and memory. (EAs) → Rd MOVFPE* Rs → (EAs) MOVTPE* @SP+ → Rn Restores the data from the stack to a general register. Rn →...
Page 62 Section 2 CPU Table 2.5 Block Transfer Instructions Instruction Size Function EEPMOV.B Transfers a data block. EEPMOV.W Transfers byte data from a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4 or R4L.
Page 63 Section 2 CPU Table 2.6 Arithmetic Operation Instructions Instruction Size Function (EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd) B/W/L Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data cannot be subtracted from byte data in a general register.
Page 64 Section 2 CPU Instruction Size Function Rd ÷ Rs → Rd DIVXU Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Page 65 Section 2 CPU Instruction Size Function  Rs → MAC LDMAC Loads data from a general register to the MAC.  MAC → Rd STMAC Stores data from the MAC to a general register. Table 2.7 Logic Operation Instructions Instruction Size Function (EAd) ∧...
Page 66 Section 2 CPU Table 2.8 Shift Operation Instructions Instruction Size Function (EAd) (shift) → (EAd) SHLL B/W/L SHLR Performs a logical shift on the contents of a general register or a memory location. The contents of a general register or a memory location can be shifted by 1, 2, 4, 8, or 16 bits.
Page 67 Section 2 CPU Instruction Size Function if cc, 0 → (<bit-No.> of <EAd>) BCLR/cc If the specified condition is satisfied, this instruction clears a specified bit in a memory location to 0. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register.
Page 68 Section 2 CPU Instruction Size Function C ⊕ [∼ (<bit-No.> of <EAd>)] → C BIXOR Logically exclusive-ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag.
Page 69 Section 2 CPU Table 2.10 Branch Instructions Instruction Size Function BRA/BS Tests a specified bit in memory location contents. If the specified condition is satisfied, execution branches to a specified address. BRA/BC BSR/BS Tests a specified bit in memory location contents. If the specified condition is satisfied, execution branches to a subroutine at a specified BSR/BC address.
Page 70 Section 2 CPU Table 2.11 System Control Instructions Instruction Size Function  TRAPA Starts trap-instruction exception handling.  Returns from an exception-handling routine.  RTE/L Returns from an exception-handling routine, restoring data from the stack to general registers.  SLEEP Causes a transition to a power-down state.
Page 71: Basic Instruction Formats
Section 2 CPU 2.7.3 Basic Instruction Formats The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.14 shows examples of instruction formats.
Page 72: Addressing Modes And Effective Address Calculation
Section 2 CPU Addressing Modes and Effective Address Calculation The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Page 73: Register Direct-Rn
Section 2 CPU 2.8.1 Register Direct—Rn The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the register field in the instruction code. R0H to R7H and R0L to R7L can be specified as 8-bit registers.
Page 74: Register Indirect With Post-Increment, Pre-Decrement, Pre-Increment, Or Post-Decrement-@Ern+, @−Ern, @+Ern, Or @Ern
Section 2 CPU 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn− Register indirect with post-increment—@ERn+ The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field in the instruction code. After the memory location is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register.
Page 75: Absolute Address-@Aa:8, @Aa:16, @Aa:24, Or @Aa:32
Section 2 CPU Example 1: MOV.W R0, @ER0+ When ER0 before execution is H'12345678, H'567A is written at H'12345678. Example 2: MOV.B @ER0+, @ER0+ When ER0 before execution is H'00001000, H'00001000 is read and the contents is written at H'00001001. After execution, ER0 is H'00001002.
Page 76: Immediate-#Xx:8, #Xx:16, Or #Xx:32
Section 2 CPU Table 2.13 shows the accessible absolute address ranges. Table 2.13 Absolute Address Access Ranges Normal Middle Advanced Maximum Absolute Address Mode Mode Mode Mode Data area 8 bits A consecutive 256-byte area (the upper address bits are set in SBR) (@aa:8) 16 bits H'0000 to H'FFFF...
Page 77: Program-Counter Relative-@(D:8, Pc) Or @(D:16, Pc)
Section 2 CPU 2.8.8 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address, which is the sum of an 8- or 16-bit displacement in the instruction code and the 32-bit address of the PC contents.
Page 78: Extended Memory Indirect-@@Vec:7
Section 2 CPU Figure 2.15 shows an example of specification of a branch address using this addressing mode. Reserved Specified Specified Branch address by @aa:8 by @aa:8 Branch address (a) Normal Mode (b) Advanced Mode Figure 2.15 Branch Address Specification in Memory Indirect Mode 2.8.11 Extended Memory Indirect—@@vec:7 This mode is used in the JMP and JSR instructions.
Page 79 Section 2 CPU Table 2.14 Effective Address Calculation for Transfer and Operation Instructions Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Immediate Register direct Register indirect General register contents Register indirect with 16-bit displacement General register contents disp disp Sign extension...
Page 80: Mova Instruction
Section 2 CPU Table 2.15 Effective Address Calculation for Branch Instructions Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Register indirect General register contents Program-counter relative with 8-bit displacement PC contents Sign extension disp disp Program-counter relative with 16-bit displacement PC contents Sign extension disp...
Page 81: Processing States
Section 2 CPU Processing States The H8SX CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and program stop state. Figure 2.16 indicates the state transitions. • Reset state In this state the CPU and internal peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state.
Page 82 Section 2 CPU Reset state* RES = high RES = low Exception-handling Bus-released state Interrupt state request request Request for exception End of exception handling handling Bus request End of bus request End of bus request Program execution Program stop state state SLEEP instruction A transition to the reset state occurs whenever the RES signal goes low.
Page 83: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Section 3 MCU Operating Modes Operating Mode Selection This LSI has two operating modes (modes 4 and 5). The operating mode is selected by the setting of mode pins (MD2 to MD0). Table 3.1 lists MCU operating mode settings. Table 3.1 MCU Operating Mode Settings External Data...
Page 84: Register Descriptions
Section 3 MCU Operating Modes Register Descriptions The following registers are related to the operating mode setting. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR indicates the current operating mode. When MDCR is read, the input levels in pins MD2 to MD0 are latched. These latches are released by a reset.
Page 85 Section 3 MCU Operating Modes Bit Name Initial Value R/W Descriptions  Reserved  These are read-only bits and cannot be modified.     Undefined*  Undefined*  Undefined* Note: Determined by pins MD2 to MD0. Table 3.2 Settings of Bits MSD2 to MSD0 MDCR MCU Operating...
Page 86: System Control Register (Syscr)
Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode.     Bit Name MACS FETCHMD...
Page 87 Section 3 MCU Operating Modes Initial Bit Name Value Descriptions  Reserved This bit is always read as 0. The write value should always be 0. EXPE External Bus Mode Enable Undefined* Selects external bus mode. In external extended mode, this bit is fixed at 1 and cannot be changed.
Page 88: Operating Mode Descriptions
Section 3 MCU Operating Modes Operating Mode Descriptions 3.3.1 Mode 4 The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the on- chip ROM is disabled. The initial bus mode immediately after a reset is 16 bits, with 16-bit access to all areas. Ports D, E, and F function as an address bus, ports H and I function as a data bus, and parts of ports A and B function as bus control signals.
Page 89: Pin Functions
Section 3 MCU Operating Modes 3.3.3 Pin Functions Table 3.3 lists the pin functions in each operating mode. Table 3.3 Pin Functions in Each Operating Mode (Advanced Mode) Port Mode 4 Mode 5 Port A P/C* P/C* PA6, PA4 P/C* P/C* PA2 to PA0 P*/C...
Page 90: Address Map
Section 3 MCU Operating Modes Address Map 3.4.1 Address Map (Advanced Mode) Figure 3.1 shows the address map. Modes 4, 5 On-chip ROM disabled extended mode (Advanced mode) H'000000 External address space H'FD9000 (Access prohibited space) H'FDC000 External address space H'FF0000 (Access prohibited space)
Page 91: Section 4 Exception Handling
Section 4 Exception Handling Section 4 Exception Handling Exception Handling Types and Priority As table 4.1 indicates, exception handling is caused by a reset, a trace, an address error, an interrupt, a trap instruction, a sleep instruction, and an illegal instruction (general illegal instruction or slot illegal instruction).
Page 92: Exception Sources And Exception Handling Vector Table
Section 4 Exception Handling Exception Sources and Exception Handling Vector Table Different vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the contents of the vector base register (VBR) and vector table address offset of the vector number.
Page 93 Section 4 Exception Handling Vector Table Address Offset* Advanced, Middle* Exception Source Vector Number Normal Mode* Maximum* Modes Reserved for system use H'0026 to H'0027 H'004C to H'004F    H'002E to H'002F H'005C to H'005F User area (open space) H'0030 to H'0031 H'0060 to H'0063 ...
Page 94: Reset
Section 4 Exception Handling Table 4.3 Calculation Method of Exception Handling Vector Table Address Exception Source Calculation Method of Vector Table Address Reset, CPU address error Vector table address = (vector table address offset) Vector table address = VBR + (vector table address offset) Other than above [Legend] VBR: Vector base register...
Page 95: Interrupts After Reset
Section 4 Exception Handling 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
Page 96 Section 4 Exception Handling Internal First instruction Vector fetch operation prefetch Bφ Address bus HWR, LWR High D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2)(4)) (6) First instruction in the exception handling routine Note: * Seven program wait cycles are inserted.
Page 97: Traces Exception Handling
Section 4 Exception Handling Traces Exception Handling Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit must be cleared.
Page 98: Address Error
Section 4 Exception Handling Address Error 4.5.1 Address Error Source Instruction fetch, stack operation, or data read/write shown in table 4.5 may cause an address error. Table 4.5 Bus Cycle and Address Error Bus Cycle Type Bus Master Description Address Error Instruction Fetches instructions from even addresses No (normal)
Page 99: Address Error Exception Handling
Section 4 Exception Handling 4.5.2 Address Error Exception Handling When an address error occurs, address error exception handling starts after the bus cycle causing the address error ends and current instruction execution completes. The address error exception handling is as follows: 1.
Page 100: Interrupts
Section 4 Exception Handling Interrupts 4.6.1 Interrupt Sources Interrupt sources are NMI, IRQ0 to IRQ11, and on-chip peripheral modules, as shown in table 4.7. Table 4.7 Interrupt Sources Type Source Number of Sources NMI pin (external input) Pins IRQ0 to IRQ11 (external input) IRQ0 to IRQ11 On-chip Watchdog timer (WDT)
Page 101: Instruction Exception Handling
Section 4 Exception Handling Instruction Exception Handling There are three instructions that cause exception handling: trap instruction, sleep instruction, and illegal instruction. 4.7.1 Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state.
Page 102: Sleep Instruction Exception Handling
Section 4 Exception Handling 4.7.2 Sleep Instruction Exception Handling The sleep instruction exception handling starts when a sleep instruction is executed with the SSBY bit in SBYCR set to 0 and the SLPIE bit in SBYCR set to 1. The sleep instruction exception handling can always be executed in the program execution state.
Page 103: Exception Handling By Illegal Instruction
Section 4 Exception Handling 4.7.3 Exception Handling by Illegal Instruction The illegal instructions are general illegal instructions and slot illegal instructions. The exception handling by the general illegal instruction starts when an undefined code is executed. The exception handling by the slot illegal instruction starts when a particular instruction (e.g. its code length is two words or more, or it changes the PC contents) at a delay slot (immediately after a delayed branch instruction) is executed.
Page 104: Stack Status After Exception Handling
Section 4 Exception Handling Stack Status after Exception Handling Figure 4.3 shows the stack after completion of exception handling. Advanced mode Reserved* PC (24 bits) PC (24 bits) Interrupt control mode 0 Interrupt control mode 2 Note: * Ignored on return. Figure 4.3 Stack Status after Exception Handling Rev.2.00 Jun.
Page 105: Usage Note
Section 4 Exception Handling Usage Note When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W (or MOV.W Rn, @-SP)
Page 106 Section 4 Exception Handling Rev.2.00 Jun. 28, 2007 Page 84 of 666 REJ09B0311-0200...
Page 107: Section 5 Interrupt Controller
Section 5 Interrupt Controller Section 5 Interrupt Controller Features • Two interrupt control modes Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the interrupt control register (INTCR). • Priority can be assigned by the interrupt priority register (IPR) IPR provides for setting interrupt priory.
Page 108 Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTM1, INTM0 INTCR NMIEG I2 to I0 interrupt request NMI input NMI input unit vector IRQ input IRQ input unit Priority determination ISCR SSIER Internal interrupt sources WOVI Source selecter...
Page 109: Input/Output Pins
Section 5 Interrupt Controller Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name Function Input Nonmaskable External Interrupt Rising or falling edge can be selected. IRQ11 to IRQ0 Input Maskable External Interrupts Rising, falling, or both edges, or level sensing, can be selected.
Page 110: Interrupt Control Register (Intcr)
Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI.      Bit Name INTM1 INTM0 NMIEG Initial Value Initial Bit Name Value Description  7, 6 All 0 Reserved These are read-only bits and cannot be modified.
Page 111: Cpu Priority Control Register (Cpupcr)
Section 5 Interrupt Controller 5.3.2 CPU Priority Control Register (CPUPCR) CPUPCR sets whether or not the CPU has priority over the DTC. The interrupt exception handling by the CPU can be given priority over that of the DTC transfer. The priority level of the DTC is set by bits DTCP2 to DTCP0 in CPUPCR.
Page 112: Interrupt Priority Registers A To C, E To H, K, And L (Ipra To Iprc, Ipre To Iprh, Iprk, And Iprl)
Section 5 Interrupt Controller Initial Bit Name Value Description CPUP2 R/(W)* CPU Priority Level 2 to 0 CPUP1 R/(W)* These bits set the CPU priority level. When the CPUPCE is set to 1, the CPU priority control function CPUP0 R/(W)* becomes valid and the priority of CPU processing is assigned in accordance with the settings of bits CPUP2 to CPUP0.
Page 113 Section 5 Interrupt Controller Initial Bit Name Value Description  Reserved This is a read-only bit and cannot be modified. IPR14 Sets the priority level of the corresponding interrupt source. IPR13 000: Priority level 0 (lowest) IPR12 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4...
Page 114: Irq Enable Register (Ier)
Section 5 Interrupt Controller Initial Bit Name Value Description IPR6 Sets the priority level of the corresponding interrupt source. IPR5 000: Priority level 0 (lowest) IPR4 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest)
Page 115 Section 5 Interrupt Controller Initial Bit Name Value Description  15 to 12 All 0 Reserved These bits are always read as 0. The write value should always be 0. IRQ11E IRQ11 Enable The IRQ11 interrupt request is enabled when this bit is IRQ10E IRQ10 Enable The IRQ10 interrupt request is enabled when this bit is...
Page 116: Irq Sense Control Registers H And L (Iscrh, Iscrl)
Section 5 Interrupt Controller 5.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH and ISCRL select the source that generates an interrupt request on pins IRQ11 to IRQ0. Upon changing the setting of ISCR, IRQnF (n = 0 to 11) in ISR is often set to 1 accidentally through an internal operation.
Page 117 Section 5 Interrupt Controller • ISCRH Initial Bit Name Value Description 15 to 8  All 0 Reserved These bits are always read as 0. The write value should always be 0. IRQ11SR IRQ11 Sense Control Rise IRQ11 Sense Control Fall IRQ11SF 00: Interrupt request generated by low level of IRQ11 01: Interrupt request generated at falling edge of IRQ11...
Page 118 Section 5 Interrupt Controller • ISCRL Initial Bit Name Value Description IRQ7SR IRQ7 Sense Control Rise IRQ7 Sense Control Fall IRQ7SF 00: Interrupt request generated by low level of IRQ7 01: Interrupt request generated at falling edge of IRQ7 10: Interrupt request generated at rising edge of IRQ7 11: Interrupt request generated at both falling and rising edges of IRQ7 IRQ6SR...
Page 119 Section 5 Interrupt Controller Initial Bit Name Value Description IRQ3SR IRQ3 Sense Control Rise IRQ3 Sense Control Fall IRQ3SF 00: Interrupt request generated by low level of IRQ3 01: Interrupt request generated at falling edge of IRQ3 10: Interrupt request generated at rising edge of IRQ3 11: Interrupt request generated at both falling and rising edges of IRQ3 IRQ2SR...
Page 120: Irq Status Register (Isr)
Section 5 Interrupt Controller 5.3.6 IRQ Status Register (ISR) ISR is an IRQ11 to IRQ0 interrupt request register.     Bit Name IRQ11F IRQ10F IRQ9F IRQ8F Initial Value R/(W)* R/(W)* R/(W)* R/(W)* Bit Name IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F...
Page 121: Software Standby Release Irq Enable Register (Ssier)
Section 5 Interrupt Controller 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects pins used to leave software standby mode from pins IRQ11 to IRQ0. The IRQ interrupt used to leave software standby mode should not be set as the DTC activation source.
Page 122: Interrupt Sources
Section 5 Interrupt Controller Interrupt Sources 5.4.1 External Interrupts There are thirteen external interrupts: NMI and IRQ11 to IRQ0. These interrupts can be used to leave software standby mode. NMI Interrupts Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the settings of the CPU interrupt mask bits.
Page 123: Internal Interrupts
Section 5 Interrupt Controller A block diagram of interrupts IRQn is shown in figure 5.2. IRQnE Corresponding bit IRQnSF, IRQnSR in ICR IRQnF IRQn interrupt request Edge/level Input buffer detection circuit IRQn input Clear signal [Legend] n = 14 to 0 Figure 5.2 Block Diagram of Interrupts IRQn When the IRQ sensing control in ISCR is set to a low level of signal IRQn, the level of IRQn should be held low until an interrupt handling starts.
Page 124: Interrupt Exception Handling Vector Table
Section 5 Interrupt Controller Interrupt Exception Handling Vector Table Table 5.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. In the default priority order, a lower vector number corresponds to a higher priority. When interrupt control mode 2 is set, priority levels can be changed by setting the IPR contents. The priority for interrupt sources allocated to the same level in IPR follows the default priority, that is, they are fixed.
Page 125 Section 5 Interrupt Controller Vector Vector Address Classification Interrupt Source Number Offset* Priority Activation    Reserved for system use H'0148 High  H'014C  H'015C  H'0154 H'0158 IPRF10 to IPRF8    Reserved for system use H'015C TPU_0 TGI0A...
Page 126 Section 5 Interrupt Controller Vector Vector Address Classification Interrupt Source Number Offset* Priority Activation    Reserved for system use H'01C8 High  H'01CC TMR_0 CMI0A H'01D0 IPRH14 to IPRH12 CMI0B H'01D4  OV0I H'01D8 TMR_1 CMI1A H'01DC IPRH10 to IPRH8 CMI1B H'01E0 ...
Page 127 Section 5 Interrupt Controller Vector Vector Address Classification Interrupt Source Number Offset* Priority Activation  SCI_0 ERI0 H'0240 IPRK6 to IPRK4 High RXI0 H'0244 TXI0 H'0248  TEI0 H'024C  SCI_1 ERI1 H'0250 IPRK2 to IPRK0 RXI1 H'0254 TXI1 H'0258 ...
Page 128: Interrupt Control Modes And Interrupt Operation
Section 5 Interrupt Controller Interrupt Control Modes and Interrupt Operation The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2.
Page 129 Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution state Interrupt generated? I = 0 Pending...
Page 130: Interrupt Control Mode 2
Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the interrupt mask level (I2 to I0 bits) in EXR of the CPU and the IPR setting. There are eight levels in mask control.
Page 131 Section 5 Interrupt Controller Program execution state Interrupt generated? Level 7 interrupt? Level 6 interrupt? Mask level 6 or below? Level 1 interrupt? Mask level 5 or below? Mask level 0? Save PC, CCR, and EXR Pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine...
Page 132: Interrupt Exception Handling Sequence
Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example is for the case where interrupt control mode 0 is set in maximum mode, and the program area and stack area are in on- chip memory.
Page 133: Interrupt Response Times
Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times – the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols for execution states used in table 5.4 are explained in table 5.5. The stack area in on-chip RAM enables high-speed processing.
Page 134: Dtc Activation By Interrupt
Section 5 Interrupt Controller Table 5.5 Number of Execution States in Interrupt Handling Routine Object of Access External Device 8-Bit Bus 16-Bit Bus On-Chip 2-State 3-State 2-State 3-State Symbol Memory Access Access Access Access Vector fetch S 12 + 4m 6 + 2m Instruction fetch S 6 + 2m...
Page 135 Section 5 Interrupt Controller Figure 5.6 shows a block diagram of the DTC and interrupt controller. Clear signal DTCER Select signal DTC activation request Interrupt request vector number On-chip DTC control peripheral Clear signal circuit Interrupt request clear signal module DTC/CPU select CPU interrupt request...
Page 136 Section 5 Interrupt Controller Operation Order If the same interrupt is selected as both the DTC activation source and CPU interrupt source, the CPU interrupt exception handling is performed after the DTC data transfer. If the same interrupt is selected as the DTC activation source or CPU interrupt source, respective operations are performed independently.
Page 137: Cpu Priority Control Function Over Dtc
Section 5 Interrupt Controller CPU Priority Control Function Over DTC The interrupt controller has a function to control the priority between the DTC and the CPU by assigning a priority levels to the DTC and CPU. Since the priority level can automatically be assigned to the CPU on an interrupt occurrence, it is possible to execute the CPU interrupt exception handling prior to the DTC transfer.
Page 138 Section 5 Interrupt Controller Table 5.7 shows the CPU priority control. Table 5.7 CPU Priority Control Control Status Interrupt Control Interrupt Interrupt IPSETE in Updating of CPUP2 Mode Priority Mask Bit CPUPCR CPUP2 to CPUP0 to CPUP0 Default I = any B'111 to B'000 Enabled I = 0...
Page 139: Usage Notes
Section 5 Interrupt Controller Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask the interrupt, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction.
Page 140: Instructions That Disable Interrupts
Section 5 Interrupt Controller 5.8.2 Instructions that Disable Interrupts Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.
Page 141: Interrupts Source Flag Of Peripheral Modules
Section 5 Interrupt Controller 5.8.6 Interrupts Source Flag of Peripheral Modules To clear an interrupt source flag by the CPU using an interrupt function of a peripheral module, the flag must be read from after clearing within the interrupt processing routine. This makes the request signal synchronized with the peripheral module clock.
Page 142 Section 5 Interrupt Controller Rev.2.00 Jun. 28, 2007 Page 120 of 666 REJ09B0311-0200...
Page 143: Section 6 Bus Controller (Bsc)
Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters;...
Page 144 Section 6 Bus Controller (BSC) • Idle cycle insertion Idle cycles can be inserted between external read accesses to different areas. Idle cycles can be inserted before the external write access after an external read access. Idle cycles can be inserted before the external read access after an external write access. •...
Page 145 Section 6 Bus Controller (BSC) A block diagram of the bus controller is shown in figure 6.1. CPU address bus CS7 to CS0 Address Area decoder DTC address bus selecter Internal bus Internal bus External bus control unit control signals control signals External bus control unit...
Page 146: Register Descriptions
Section 6 Bus Controller (BSC) Register Descriptions The bus controller has the following registers. • Bus width control register (ABWCR) • Access state control register (ASTCR) • Wait control register A (WTCRA) • Wait control register B (WTCRB) • Read strobe timing control register (RDNCR) •...
Page 147 Section 6 Bus Controller (BSC) Initial Bit Name Value* Description ABWH7 Area 7 to 0 Bus Width Control ABWH6 These bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space. ABWH5 ABWHn ABWLn (n = 7 to 0) ABWH4 ×...
Page 148: Access State Control Register (Astcr)
Section 6 Bus Controller (BSC) 6.2.2 Access State Control Register (ASTCR) ASTCR designates each area in the external address space as either 2-state access space or 3-state access space and enables/disables wait cycle insertion. Bit Name AST7 AST6 AST5 AST4 AST3 AST2 AST1...
Page 149: Wait Control Registers A And B (Wtcra, Wtcrb)
Section 6 Bus Controller (BSC) 6.2.3 Wait Control Registers A and B (WTCRA, WTCRB) WTCRA and WTCRB select the number of program wait cycles for each area in the external address space. • WTCRA   Bit Name Initial Value ...
Page 150 Section 6 Bus Controller (BSC) • WTCRA Initial Bit Name Value Description  Reserved This is a read-only bit and cannot be modified. Area 7 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 7 while bit AST7 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted...
Page 151 Section 6 Bus Controller (BSC) Initial Bit Name Value Description Area 5 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 5 while bit AST5 in ASTCR is 1. 000: Program cycle wait not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted...
Page 152 Section 6 Bus Controller (BSC) • WTCRB Initial Bit Name Value Description  Reserved This is a read-only bit and cannot be modified. Area 3 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 3 while bit AST3 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted...
Page 153 Section 6 Bus Controller (BSC) Initial Bit Name Value Description Area 1 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 1 while bit AST1 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted...
Page 154: Read Strobe Timing Control Register (Rdncr)
Section 6 Bus Controller (BSC) 6.2.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the negation timing of the read strobe signal (RD) when reading the external address spaces specified as a basic bus interface or the address/data multiplexed I/O interface. Bit Name RDN7 RDN6...
Page 155: Cs Assertion Period Control Registers (Csacr)
Section 6 Bus Controller (BSC) Bus cycle Bφ RDNn = 0 Data RDNn = 1 Data (n = 7 to 0) Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) CS Assertion Period Control Registers (CSACR) 6.2.5 CSACR selects whether or not the assertion periods of the chip select signals (CSn) and address signals for the basic bus, byte-control SRAM, burst ROM, and address/data multiplexed I/O interface are to be extended.
Page 156 Section 6 Bus Controller (BSC) Initial Bit Name Value Description CS and Address Signal Assertion Period Control 1 CSXH7 CSXH6 These bits specify whether or not the Th cycle is to be inserted (see figure 6.3). When an area for which bit CSXH5 CSXHn is set to 1 is accessed, one Th cycle, in which the CSXH4...
Page 157: Idle Control Register (Idlcr)
Section 6 Bus Controller (BSC) Bus cycle Bφ Address RD/WR Read Data bus Read data LHWR, LLWR Write Write data Data bus Figure 6.3 CS and Address Assertion Period Extension (Example of Basic Bus Interface, 3-State Access Space, and RDNn = 0) 6.2.6 Idle Control Register (IDLCR) IDLCR specifies the idle cycle insertion conditions and the number of idle cycles.
Page 158 Section 6 Bus Controller (BSC) Initial Bit Name Value Description  Reserved This bit is always read as 1. The write value should always be 1. IDLS2 Idle Cycle Insertion 2 Inserts an idle cycle between the bus cycles when the external write cycle is followed by external read cycle.
Page 159: Bus Control Register 1 (Bcr1)
Section 6 Bus Controller (BSC) Initial Bit Name Value Description IDLSEL7 Idle Cycle Number Select IDLSEL6 Specifies the number of idle cycles to be inserted for each area for the idle insertion condition specified by IDLSEL5 IDLS1 and IDLS0. IDLSEL4 0: Number of idle cycles to be inserted for area n is IDLSEL3 specified by IDLCA1 and IDLCA0.
Page 160 Section 6 Bus Controller (BSC) Initial Bit Name Value Description BREQO Pin Enable BREQOE Controls outputting the bus request signal (BREQO) to the external bus master in the external bus released state when an internal bus master performs an external address space access.
Page 161: Bus Control Register 2 (Bcr2)
Section 6 Bus Controller (BSC) 6.2.8 Bus Control Register 2 (BCR2) BCR2 is used for bus arbitration control of the CPU and DTC, and enabling/disabling of the write data buffer function to the peripheral modules.      ...
Page 162: Endian Control Register (Endiancr)
Section 6 Bus Controller (BSC) 6.2.9 Endian Control Register (ENDIANCR) ENDIANCR selects the endian format for each area of the external address space. Though the data format of this LSI is big endian, data can be transferred in the little endian format during external address space access.
Page 163: Sram Mode Control Register (Sramcr)
Section 6 Bus Controller (BSC) 6.2.10 SRAM Mode Control Register (SRAMCR) SRAMCR specifies the bus interface of each area in the external address space as a basic bus interface or a byte control SRAM interface. In areas specified as 8-bit access space by ABWCR, the SRAMCR setting is ignored and the byte control SRAM interface cannot be specified.
Page 164: Burst Rom Interface Control Register (Bromcr)
Section 6 Bus Controller (BSC) 6.2.11 Burst ROM Interface Control Register (BROMCR) BROMCR specifies the burst ROM interface.   Bit Name BSRM0 BSTS02 BSTS01 BSTS00 BSWD01 BSWD00 Initial Value   Bit Name BSRM1 BSTS12 BSTS11 BSTS10 BSWD11 BSWD10 Initial Value Initial Bit Name...
Page 165 Section 6 Bus Controller (BSC) Initial Bit Name Value Description BSWD01 Area 0 Burst Word Number Select BSWD00 Selects the number of words in burst access to the area 0 burst ROM interface 00: Up to 4 words (8 bytes) 01: Up to 8 words (16 bytes) 10: Up to 16 words (32 bytes) 11: Up to 32 words (64 bytes)
Page 166: Address/Data Multiplexed I/O Control Register (Mpxcr)
Section 6 Bus Controller (BSC) 6.2.12 Address/Data Multiplexed I/O Control Register (MPXCR) MPXCR specifies the address/data multiplexed I/O interface.    Bit Name MPXE7 MPXE6 MPXE5 MPXE4 MPXE3 Initial Value        Bit Name ADDEX Initial Value Initial...
Page 167: Bus Configuration
Section 6 Bus Controller (BSC) Bus Configuration Figure 6.4 shows the internal bus configuration of this LSI. The internal bus of this LSI consists of the following three types. • Internal system bus A bus that connects the CPU, DTC, on-chip RAM, internal peripheral bus, and external access bus.
Page 168: Multi-Clock Function And Number Of Access Cycles
Section 6 Bus Controller (BSC) Multi-Clock Function and Number of Access Cycles The internal functions of this LSI operate synchronously with the system clock (Iφ), the peripheral module clock (Pφ), or the external bus clock (Bφ). Table 6.1 shows the synchronization clock and their corresponding functions.
Page 169 Section 6 Bus Controller (BSC) If the frequencies of Iφ, Pφ and Bφ are different, the start of bus cycle may not synchronize with Pφ or Bφ according to the bus cycle initiation timing. In this case, clock synchronization cycle (Tsy) is inserted at the beginning of each bus cycle.
Page 170 Section 6 Bus Controller (BSC) Divided clock synchronization cycle Iφ Bφ Address Read D15 to D8 D7 to D0 LHWR LLWR Write D15 to D8 D7 to D0 RD/WR Figure 6.5 System Clock: External Bus Clock = 4:1, External 2-State Access Rev.2.00 Jun.
Page 171 Section 6 Bus Controller (BSC) Divided clock synchronization cycle Iφ Bφ Address Read D15 to D8 D7 to D0 LHWR LLWR Write D15 to D8 D7 to D0 RD/WR Figure 6.6 System Clock: External Bus Clock = 2:1, External 3-State Access Rev.2.00 Jun.
Page 172: External Bus
Section 6 Bus Controller (BSC) External Bus 6.5.1 Input/Output Pins Table 6.2 shows the pin configuration of the bus controller and table 6.3 shows the pin functions on each interface. Table 6.2 Pin Configuration Name Symbol Function Bus cycle start Output Signal indicating that the bus cycle has started...
Page 173 Section 6 Bus Controller (BSC) Name Symbol Function LLWR/LLB Output • Low-low write/lower-lower byte Strobe signal indicating that the basic select bus, burst ROM, or address/data multiplexed I/O space is written to, and the lower byte (D7 to D0) of data bus is enabled •...
Page 174 Section 6 Bus Controller (BSC) Table 6.3 Pin Functions in Each Interface Byte Address/Data Control Burst Multiplexed Initial State Basic Bus SRAM Single- Pin Name Remarks Chip Output Output  Bφ Output Output        ...
Page 175: Area Division
Section 6 Bus Controller (BSC) 6.5.2 Area Division The bus controller divides the 16-Mbyte address space into eight areas, and performs bus control for the external address space in area units. Chip select signals (CS0 to CS7) can be output for each area.
Page 176: Chip Select Signals
Section 6 Bus Controller (BSC) 6.5.3 Chip Select Signals This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when the corresponding external address space area is accessed. Figure 6.8 shows an example of CSn (n = 0 to 7) signal output timing.
Page 177: External Bus Interface
Section 6 Bus Controller (BSC) Area 5 access Area 6 access Bφ Output waveform Address bus Area 5 access Area 6 access Figure 6.9 Timing When CS Signal is Output to the Same Pin 6.5.4 External Bus Interface The type of the external bus interfaces, bus width, endian format, number of access cycles, and strobe assert/negate timings can be set for each area in the external address space.
Page 178 Section 6 Bus Controller (BSC) Table 6.5 Areas Specifiable for Each Interface Areas Related Interface Registers Basic interface SRAMCR Byte control SRAM interface       Burst ROM interface BROMCR    Address/data multiplexed I/O MPXCR interface Bus Width A bus width of 8 or 16 bits can be selected with ABWCR.
Page 179 Section 6 Bus Controller (BSC) Number of Access Cycles Basic Bus Interface The number of access cycles in the basic bus interface can be specified as two or three cycles by the ASTCR. An area specified as 2-state access is specified as 2-state access space; an area specified as 3-state access is specified as 3-state access space.
Page 180 Section 6 Bus Controller (BSC) (d) Address/data multiplexed I/O interface The number of access cycles in data cycle of the address/data multiplexed I/O interface is the same as that in the basic bus interface. The number of access cycles in address cycle can be specified as two or three cycles by the ADDEX bit in MPXCR.
Page 181: Area And External Bus Interface
Section 6 Bus Controller (BSC) 6.5.5 Area and External Bus Interface Area 0 Area 0 includes on-chip ROM*. All of area 0 is used as external address space in on-chip ROM disabled extended mode, and the space excluding on-chip ROM is external address space in on- chip ROM enabled extended mode.
Page 182 Section 6 Bus Controller (BSC) Table 6.8 Area 1 External Interface Register Setting Interface BSRM1 of BROMCR BCSEL1 of SRAMCR Basic bus interface Byte control SRAM interface Burst ROM interface Setting prohibited Area 2 In externally extended mode, all of area 2 is external address space. When area 2 external address space is accessed, the CS2 signal can be output.
Page 183 Section 6 Bus Controller (BSC) Table 6.10 Area 3 External Interface Register Setting Interface MPXE3 of MPXCR BCSEL3 of SRAMCR Basic bus interface Byte control SRAM interface Address/data multiplexed I/O interface Setting prohibited Area 4 In externally extended mode, all of area 4 is external address space. When area 4 external address space is accessed, the CS4 signal can be output.
Page 184 Section 6 Bus Controller (BSC) When area 5 external address space is accessed, the CS5 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 5 by the MPXE5 bit in MPXCR and the BCSEL5 bit in SRAMCR.
Page 185: Endian And Data Alignment
Section 6 Bus Controller (BSC) Area 7 Area 7 includes internal I/O registers. In external extended mode, area 7 other than internal I/O register area is external address space. When area 7 external address space is accessed, the CS7 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 7 by the MPXE7 bit in MPXCR and the BCSEL7 bit in SRAMCR.
Page 186 Section 6 Bus Controller (BSC) 8-Bit Access Space With the 8-bit access space, the lower byte data bus (D7 to D0) is always used for access. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses.
Page 187 Section 6 Bus Controller (BSC) 16-Bit Access Space With the 16-bit access space, the upper byte data bus (D15 to D8) and lower byte data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word.
Page 188 Section 6 Bus Controller (BSC) Strobe signal LHWR/LUB LLWR/LLB Data bus Access Access Access D8 D7 Size Count Address Data Size Cycle Even Byte Byte (2n) Byte (2n+1) Even Word Word (2n) Byte (2n+1) Byte Longword Even Word (2n) Word Byte (2n+1) Word...
Page 189: Basic Bus Interface
Section 6 Bus Controller (BSC) Basic Bus Interface The basic bus interface can be connected directly to the ROM and SRAM. The bus specifications can be specified by the ABWCR, ASTCR, WTCRA, WTCRB, RDNCR, CSACR, and ENDINCR. 6.6.1 Data Bus Data sizes for the CPU and other internal bus masters are byte, word, and longword.
Page 190: Basic Timing
Section 6 Bus Controller (BSC) 6.6.3 Basic Timing This section describes the basic timing when the data is specified as big endian. 16-Bit 2-State Access Space Figures 6.14 to 6.16 show the bus timing of 16-bit 2-state access space. When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even addresses access, and the lower byte data bus (D7 to D0) is used for odd addresses.
Page 191 Section 6 Bus Controller (BSC) Bus cycle Bφ Address D15 to D8 Invalid Read D7 to D0 Valid LHWR High level LLWR Write D15 to D8 High-Z D7 to D0 Valid RD/WR Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.15 16-Bit 2-State Access Space Bus Timing (Byte Access for Odd Address) Rev.2.00 Jun.
Page 192 Section 6 Bus Controller (BSC) Bus cycle Bφ Address Valid D15 to D8 Read Valid D7 to D0 LHWR LLWR Write Valid D15 to D8 Valid D7 to D0 RD/WR Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.16 16-Bit 2-State Access Space Bus Timing (Word Access for Even Address) Rev.2.00 Jun.
Page 193 Section 6 Bus Controller (BSC) 16-Bit 3-State Access Space Figures 6.17 to 6.19 show the bus timing of 16-bit 3-state access space. When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even addresses, and the lower byte data bus (D7 to D0) is used for odd addresses. Wait cycles can be inserted.
Page 194 Section 6 Bus Controller (BSC) Bus cycle Bφ Address Read D15 to D8 Invalid D7 to D0 Valid High level LHWR LLWR Write D15 to D8 High-Z D7 to D0 Valid RD/WR Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.18 16-Bit 3-State Access Space Bus Timing (Word Access for Odd Address) Rev.2.00 Jun.
Page 195 Section 6 Bus Controller (BSC) Bus cycle Bφ Address Valid Read D15 to D8 Valid D7 to D0 LHWR LLWR Write D15 to D8 Valid D7 to D0 Valid RD/WR Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.19 16-Bit 3-State Access Space Bus Timing (Word Access for Even Address) Rev.2.00 Jun.
Page 196: Wait Control
Section 6 Bus Controller (BSC) 6.6.4 Wait Control This LSI can extend the bus cycle by inserting wait cycles (Tw) when the external address space is accessed. There are two ways of inserting wait cycles: program wait (Tpw) insertion and pin wait (Ttw) insertion using the WAIT pin.
Page 197 Section 6 Bus Controller (BSC) Wait by program Wait by WAIT pin wait Bφ WAIT Address Read Read Data bus data LHWR, LLWR Write Data bus Write data RD/WR Notes: 1. Upward arrows indicate the timing of WAIT pin sampling. 2.
Page 198: Read Strobe (Rd) Timing
Section 6 Bus Controller (BSC) 6.6.5 Read Strobe (RD) Timing The read strobe timing can be modified in area units by setting bits RDN7 to RDN0 in RDNCR to Figure 6.21 shows an example of timing when the read strobe timing is changed in the basic bus 3- state access space.
Page 199: Extension Of Chip Select (Cs) Assertion Period
Section 6 Bus Controller (BSC) 6.6.6 Extension of Chip Select (CS) Assertion Period Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, LHWR, and LLWR. Settings can be made in CSACR to insert cycles in which only the CS, AS, and address signals are asserted before and after a basic bus space access cycle.
Page 200 Section 6 Bus Controller (BSC) Bus cycle Bφ Address Read Data bus Read data LHWR, LLWR Write Data bus Write data RD/WR Note: n = 0 to 7 Figure 6.22 Example of Timing when Chip Select Assertion Period is Extended Rev.2.00 Jun.
Page 201: Byte Control Sram Interface
Section 6 Bus Controller (BSC) Byte Control SRAM Interface The byte control SRAM interface is a memory interface for outputting a byte select strobe during a read or a write bus cycle. This interface has 16-bit data input/output pins and can be connected to the SRAM that has the upper byte select and the lower byte select strobes such as UB and LB.
Page 202: I/O Pins Used For Byte Control Sram Interface
Section 6 Bus Controller (BSC) 6.7.3 I/O Pins Used for Byte Control SRAM Interface Table 6.16 shows the pins used for the byte control SRAM interface. In the byte control SRAM interface, write strobe signals (LHWR and LLWR) are output from the byte select strobes.
Page 203: Basic Timing
Section 6 Bus Controller (BSC) 6.7.4 Basic Timing 2-State Access Space Figure 6.23 shows the bus timing when the byte control SRAM space is specified as a 2-state access space. Data buses used for 16-bit access space is the same as those in basic bus interface. No wait cycles can be inserted.
Page 204 Section 6 Bus Controller (BSC) 3-State Access Space Figure 6.24 shows the bus timing when the byte control SRAM space is specified as a 3-state access space. Data buses used for 16-bit access space is the same as those in the basic bus interface. Wait cycles can be inserted.
Page 205: Wait Control
Section 6 Bus Controller (BSC) 6.7.5 Wait Control The bus cycle can be extended for the byte control SRAM interface by inserting wait cycles (Tw) in the same way as the basic bus interface. Program Wait Insertion From 0 to 7 wait cycles can be inserted automatically between T2 cycle and T3 cycle for the 3- state access space in area units, according to the settings in WTCRA and WTCRB.
Page 206 Section 6 Bus Controller (BSC) Wait by Wait by WAIT pin program wait Bφ WAIT Address UUB, ULB RD/WR Read Data bus Read data RD/WR Write High level Data bus Write data Notes: 1. Upward arrows indicate the timing of WAIT pin sampling. 2.
Page 207: Read Strobe (Rd)
Section 6 Bus Controller (BSC) 6.7.6 Read Strobe (RD) When the byte control SRAM space is specified, the RDNCR setting for the corresponding space is invalid. The read strobe negation timing is the same timing as when RDNn = 1 in the basic bus interface. 6.7.7 Extension of Chip Select (CS) Assertion Period In the byte control SRAM interface, the extension cycles can be inserted before and after the bus...
Page 208: Data Bus
Section 6 Bus Controller (BSC) 6.8.2 Data Bus The bus width of the burst ROM space can be specified as 8-bit or16-bit burst ROM interface space according to the ABWHn and ABWLn bits (n = 0, 1) in ABWCR. For the 8-bit bus width, data bus (D7 to D0) is valid. For the 16-bit bus width, data bus (D15 to D0) is valid.
Page 209: Basic Timing
Section 6 Bus Controller (BSC) 6.8.4 Basic Timing The number of access cycles in the initial cycle (full access) on the burst ROM interface is determined by the basic bus interface settings in ABWCR, ASTCR, WTCRA, WTCRB, and bits CSXHn in CSACR (n = 0 to 7). When area 0 or area 1 designated as burst ROM space is read by the CPU, the settings in RDNCR and bits CSXTn in CSACR (n = 0 to 7) are ignored.
Page 210 Section 6 Bus Controller (BSC) Full access Burst access Bφ Upper address bus Lower address bus Data bus RD/WR Note: n = 1, 0 Figure 6.27 Example of Burst ROM Access Timing (ASTn = 0, One Burst Cycle) Rev.2.00 Jun. 28, 2007 Page 188 of 666 REJ09B0311-0200...
Page 211: Wait Control
Section 6 Bus Controller (BSC) 6.8.5 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion by the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.6.4, Wait Control.
Page 212: Address/Data Multiplex
Section 6 Bus Controller (BSC) 6.9.2 Address/Data Multiplex In the address/data multiplexed I/O space, data bus is multiplexed with address bus. Table 6.18 shows the relationship between the bus width and address output. Table 6.18 Address/Data Multiplex Data Pins Bus Width Cycle ...
Page 213: I/O Pins Used For Address/Data Multiplexed I/O Interface
Section 6 Bus Controller (BSC) 6.9.4 I/O Pins Used for Address/Data Multiplexed I/O Interface Table 6.19 shows the pins used for the address/data multiplexed I/O Interface. Table 6.19 I/O Pins for Address/Data Multiplexed I/O Interface When Byte Control SRAM is Specified Name Function...
Page 214: Basic Timing
Section 6 Bus Controller (BSC) 6.9.5 Basic Timing The bus cycle in the address/data multiplexed I/O interface consists of an address cycle and a data cycle. The data cycle is based on the basic bus interface timing specified by the ABWCR, ASTCR, WTCRA, WTCRB, RDNCR, and CSACR.
Page 215 Section 6 Bus Controller (BSC) Bus cycle Address cycle Data cycle Bφ Address bus Read D15 to D0 Address Read data LHWR LLWR Write D15 to D0 Address Write data RD/WR Note: n = 3 to 7 Figure 6.29 16-Bit Access Space Access Timing (ABWHn = 0, ABWLn = 1) Rev.2.00 Jun.
Page 216: Address Cycle Control
Section 6 Bus Controller (BSC) 6.9.6 Address Cycle Control An extension cycle (Tmaw) can be inserted between Tma1 and Tma2 cycles to extend the AH signal output period by setting the ADDEX bit in MPXCR. By inserting the Tmaw cycle, the address setup for AH and the AH minimum pulse width can be assured.
Page 217: Wait Control
Section 6 Bus Controller (BSC) 6.9.7 Wait Control In the data cycle of the address/data multiplexed I/O interface, program wait insertion and pin wait insertion by the WAIT pin are enabled in the same way as in the basic bus interface. For details, see section 6.6.4, Wait Control.
Page 218: Extension Of Chip Select (Cs) Assertion Period
Section 6 Bus Controller (BSC) 6.9.9 Extension of Chip Select (CS) Assertion Period In the address/data multiplexed interface, the extension cycles can be inserted before and after the bus cycle. For details, see section 6.6.6, Extension of Chip Select (CS) Assertion Period. Figure 6.32 shows an example of the chip select (CS) assertion period extension timing.
Page 219 Section 6 Bus Controller (BSC) Figure 6.33 shows an example of the operation. In the figure, both bus cycles A and B are read access cycles to the address/data multiplexed I/O space. An example of the data conflict is shown in (a), and an example of avoiding the data conflict by the CS assertion period extension cycle in (b).
Page 220: Idle Cycle
Section 6 Bus Controller (BSC) 6.10 Idle Cycle In this LSI, idle cycles can be inserted between the consecutive external accesses. By inserting the idle cycle, data conflicts between ROM read cycle whose output floating time is long and an access cycle from/to high-speed memory or I/O interface can be prevented.
Page 221 Section 6 Bus Controller (BSC) Table 6.20 shows the correspondence between conditions 1 to 3 and number of idle cycles to be inserted for each area. Table 6.21 shows the correspondence between the number of idle cycles to be inserted specified by settings A and B, and number of cycles to be inserted. Table 6.20 Number of Idle Cycle Insertion Selection in Each Area Bit Settings IDLSn...
Page 222 Section 6 Bus Controller (BSC) Consecutive Reads in Different Areas If consecutive reads in different areas occur while bit IDLS1 in IDLCR is set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 when bit IDSELn in IDLCR is cleared to 0, or bits IDLCB1 and IDLCB0 when bit IDLSELn is set to 1 are inserted at the start of the second read cycle (n = 0 to 7).
Page 223 Section 6 Bus Controller (BSC) Write after Read If an external write occurs after an external read while bit IDLS0 in IDLCRis set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 when bit IDSELn in IDLCR is cleared to 0 when IDLSELn = 0,or bits IDLCB1 and IDLCB0 when IDLSELn is set to 1 are inserted at the start of the write cycle (n = 0 to 7).
Page 224 Section 6 Bus Controller (BSC) Read after Write If an external read occurs after an external write while bit IDLS2 in IDLCR is set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 are inserted at the start of the read cycle (n = 0 to 7). Figure 6.36 shows an example of the operation in this case.
Page 225 Section 6 Bus Controller (BSC) External NOP Cycles and Idle Cycles In consecutive external bus accesses, in which even if the cycles that access no external space (external NOP cycles) exist, the condition of inserting idle cycles is effective. In this case, the external NOP cycles are counted as a part of the idle cycles.
Page 226 Section 6 Bus Controller (BSC) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system's load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.38. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the RD signal in bus cycle A and the CS signal in bus cycle B.
Page 227 Section 6 Bus Controller (BSC) Table 6.22 Idle Cycles in Mixed Accesses to Normal Space IDLS IDLSEL IDLCA IDLCB Previous Next Access Access 7 to 0 Idle Cycle        Normal space Normal Disabled read space read ...
Page 228: Pin States In Idle Cycle
Section 6 Bus Controller (BSC) 6.10.2 Pin States in Idle Cycle Table 6.23 shows the pin states in an idle cycle. Table 6.23 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of following bus cycle D15 to D0 High impedance CSn (n = 7 to 0) High...
Page 229: Bus Release
Section 6 Bus Controller (BSC) 6.11 Bus Release This LSI can release the external bus in response to a bus request from an external device. In the external bus released state, internal bus masters continue to operate as long as there is no external access.
Page 230: Pin States In External Bus Released State
Section 6 Bus Controller (BSC) 6.11.2 Pin States in External Bus Released State Table 6.24 shows pin states in the external bus released state. Table 6.24 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance High impedance...
Page 231: Transition Timing
Section 6 Bus Controller (BSC) 6.11.3 Transition Timing Figure 6.39 shows the timing for transition to the bus released state. External CPU cycle access cycle External bus released state Bφ Hi-Z Address bus Hi-Z Data bus Hi-Z Hi-Z Hi-Z Hi-Z LHWR, LLWR BREQ BACK...
Page 232: Internal Bus
Section 6 Bus Controller (BSC) 6.12 Internal Bus 6.12.1 Access to Internal Address Space The internal address spaces of this LSI are the on-chip RAM space and register space for the on- chip peripheral modules. The number of cycles necessary for access differs according the space. Table 6.25 shows the number of access cycles for each on-chip memory space.
Page 233: Write Data Buffer Function
Section 6 Bus Controller (BSC) 6.13 Write Data Buffer Function 6.13.1 Write Data Buffer Function for External Data Bus This LSI has a write data buffer function for the external data bus. Using the write data buffer function enables external writes and internal accesses in parallel. The write data buffer function is made available by setting the WDBE bit to 1 in BCR1.
Page 234: Write Data Buffer Function For Peripheral Modules
Section 6 Bus Controller (BSC) 6.13.2 Write Data Buffer Function for Peripheral Modules This LSI has a write data buffer function for the peripheral module access. Using the write data buffer function enables peripheral module writes and on-chip memory or external access to be executed in parallel.
Page 235: Bus Arbitration
Section 6 Bus Controller (BSC) 6.14 Bus Arbitration This LSI has bus arbiters that arbitrate bus mastership operations (bus arbitration). This LSI incorporates internal access and external access bus arbiters that can be used and controlled independently. The internal bus arbiter handles the CPU and DTC accesses. The external bus arbiter handles the external access by the CPU and DTC and external bus release request (external bus master).
Page 236: Bus Transfer Timing
Section 6 Bus Controller (BSC) 6.14.2 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority over that of the bus master that has taken control of the bus and is currently operating, the bus is not necessarily transferred immediately.
Page 237: Bus Controller Operation In Reset
Section 6 Bus Controller (BSC) Note, however, that the bus cannot be transferred in the following cases. • During transfer information read • During the first data transfer • During transfer information write back The DTC releases the bus when the consecutive transfer cycles completed. External Bus Release When the BREQ pin goes low and an external bus release request is issued while the BRLE bit in BCR1 and the ICR bit of the corresponding pin are set to 1, a bus request is sent to the bus arbiter.
Page 238 Section 6 Bus Controller (BSC) External Bus Release Function and Software Standby In this LSI, internal bus master operation does not stop even while the bus is released, as long as the program is running in on-chip RAM, etc., and no external access occurs. If a SLEEP instruction to place the chip in software standby mode is executed while the external bus is released, the transition to software standby mode is deferred and performed after the bus is recovered.
Page 239: Section 7 Data Transfer Controller (Dtc)
Section 7 Data Transfer Controller (DTC) Section 7 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated to transfer data by an interrupt request. Features • Transfer possible over any number of channels: Multiple data transfer enabled for one activation source (chain transfer) Chain transfer specifiable after data transfer (when the counter is 0) •...
Page 240 Section 7 Data Transfer Controller (DTC) Figure 7.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to the data area*. When the transfer information is allocated to the on-chip RAM, a 32-bit bus connects the DTC to the on-chip RAM, enabling 32-bit/1-state reading and writing of the DTC transfer information.
Page 241: Register Descriptions
Section 7 Data Transfer Controller (DTC) Register Descriptions DTC has the following registers. • DTC mode register A (MRA) • DTC mode register B (MRB) • DTC source address register (SAR) • DTC destination address register (DAR) • DTC transfer count register A (CRA) •...
Page 242: Dtc Mode Register A (Mra)
Section 7 Data Transfer Controller (DTC) 7.2.1 DTC Mode Register A (MRA) MRA selects DTC operating mode. MRA cannot be accessed directly by the CPU.   Bit Name Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined  ...
Page 243: Dtc Mode Register B (Mrb)
Section 7 Data Transfer Controller (DTC) 7.2.2 DTC Mode Register B (MRB) MRB selects DTC operating mode. MRB cannot be accessed directly by the CPU.   Bit Name CHNE CHNS DISEL Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined ...
Page 244 Section 7 Data Transfer Controller (DTC) Initial Bit Name Value Description  Undefined Destination Address Mode 1 and 0  Undefined Specify a DAR operation after a data transfer. 0X: DAR is fixed (DAR writeback is skipped) 10: DAR is incremented after a transfer (by 1 when Sz1 and Sz0 = B'00;...
Page 245: Dtc Source Address Register (Sar)
Section 7 Data Transfer Controller (DTC) 7.2.3 DTC Source Address Register (SAR) SAR is a 32-bit register that designates the source address of data to be transferred by the DTC. In full address mode, 32 bits of SAR are valid. In short address mode, the lower 24 bits of SAR are valid and bits 31 to 24 are ignored.
Page 246: Dtc Transfer Count Register A (Cra)
Section 7 Data Transfer Controller (DTC) 7.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal transfer mode, CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source is cleared and then an interrupt is requested to the CPU when the count reaches H'0000.
Page 247: Dtc Enable Registers A To H (Dtcera To Dtcerh)
Section 7 Data Transfer Controller (DTC) 7.2.7 DTC Enable Registers A to H (DTCERA to DTCERH) DTCER, which is comprised of eight registers, DTCERA to DTCERH, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 7.1.
Page 248: Dtc Control Register (Dtccr)
Section 7 Data Transfer Controller (DTC) 7.2.8 DTC Control Register (DTCCR) DTCCR specifies transfer information read skip.      Bit Name RCHNE Initial Value R/(W)* Note: * Only 0 can be written to clear the flag. Initial Bit Name Value Description...
Page 249: Dtc Vector Base Register (Dtcvbr)
Section 7 Data Transfer Controller (DTC) Initial Bit Name Value Description R/(W)* Transfer Stop Flag Indicates that an address error or an NMI interrupt occurs. If an address error or an NMI interrupt occurs, the DTC stops. 0: No interrupt occurs 1: An interrupt occurs [Clearing condition] •...
Page 250: Location Of Transfer Information And Dtc Vector Table
Section 7 Data Transfer Controller (DTC) Location of Transfer Information and DTC Vector Table Locate the transfer information in the data area. The start address of transfer information should be located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored during access ([1:0] = B'00.) Transfer information can be located in either short address mode (three longwords) or full address mode (four longwords).
Page 251 Section 7 Data Transfer Controller (DTC) Upper: DTCVBR Lower: H'400 + vector number × 4 Vector table Transfer information (1) DTC vector address Transfer information (1) start address Transfer information (2) start address Transfer information (2) Transfer information (n) start address 4 bytes Transfer information (n) Figure 7.3 Correspondence between DTC Vector Address and Transfer Information...
Page 252 Section 7 Data Transfer Controller (DTC) Origin of Activation Vector DTC Vector Activation Source Source Number Address Offset DTCE* Priority TPU_0 TGI0A H'560 DTCEB13 High TGI0B H'564 DTCEB12 TGI0C H'568 DTCEB11 TGI0D H'56C DTCEB10 TPU_1 TGI1A H'574 DTCEB9 TGI1B H'578 DTCEB8 TPU_2 TGI2A...
Page 253: Operation
Section 7 Data Transfer Controller (DTC) Operation The DTC stores transfer information in the data area. When activated, the DTC reads transfer information that is stored in the data area and transfers data on the basis of that transfer information. After the data transfer, it writes updated transfer information back to the data area. Since transfer information is in the data area, it is possible to transfer data over any required number of channels.
Page 254 Section 7 Data Transfer Controller (DTC) Start Match & RRS = 1 Vector number comparison Not match | RRS = 0 Read DTC vector Next transfer Read transfer information Transfer data Update transfer Update the start address information of transfer information Write transfer information CHNE = 1 CHNS = 0...
Page 255: Bus Cycle Division
Section 7 Data Transfer Controller (DTC) Table 7.3 Chain Transfer Conditions 1st Transfer 2nd Transfer Transfer Transfer CHNE CHNS DISEL Counter* CHNE CHNS DISEL Counter* DTC Transfer      Not 0 Ends at 1st transfer   ...
Page 256 Section 7 Data Transfer Controller (DTC) [Example 1: When an odd address and even address are specified in SAR and DAR, respectively, and when the data size of transfer is specified as word] Clock DTC activation request DTC request Address Vector read Transfer information Data transfer Transfer information...
Page 257: Transfer Information Read Skip Function
Section 7 Data Transfer Controller (DTC) 7.5.2 Transfer Information Read Skip Function By setting the RRS bit of DTCCR, the vector address read and transfer information read can be skipped. The current DTC vector number is always compared with the vector number of previous activation.
Page 258: Transfer Information Writeback Skip Function
Section 7 Data Transfer Controller (DTC) 7.5.3 Transfer Information Writeback Skip Function By specifying bit SM1 in MRA and bit DM1 in MRB to the fixed address mode, a part of transfer information will not be written back. This function is performed regardless of short or full address mode.
Page 259: Repeat Transfer Mode
Section 7 Data Transfer Controller (DTC) Transfer source data area Transfer destination data area Transfer Figure 7.7 Memory Map in Normal Transfer Mode 7.5.5 Repeat Transfer Mode In repeat transfer mode, one operation transfers one byte, one word, or one longword of data. By the DTS bit in MRB, either the source or destination can be specified as a repeat area.
Page 260 Section 7 Data Transfer Controller (DTC) Table 7.7 Register Function in Repeat Transfer Mode Written Back Value Register Function CRAL is not 1 CRAL is 1 Source address Incremented/decremented/fixed DTS =0: Incremented/ decremented/fixed* DTS = 1: SAR initial value Destination address Incremented/decremented/fixed DTS = 0: DAR initial value DTS =1: Incremented/ decremented/fixed*...
Page 261: Block Transfer Mode
Section 7 Data Transfer Controller (DTC) 7.5.6 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area by the DTS bit in MRB. The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords).
Page 262: Chain Transfer
Section 7 Data Transfer Controller (DTC) 7.5.7 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. Setting the CHNE and CHNS bits in MRB set to 1 enables a chain transfer only when the transfer counter reaches 0.
Page 263: Operation Timing
Section 7 Data Transfer Controller (DTC) 7.5.8 Operation Timing Figures 7.11 to 7.14 show the DTC operation timings. Clock DTC activation request DTC request Address Vector read Transfer Data transfer Transfer information information read write Figure 7.11 DTC Operation Timing (Example of Short Address Mode in Normal Transfer Mode or Repeat Transfer Mode) Clock DTC activation...
Page 264 Section 7 Data Transfer Controller (DTC) Clock DTC activation request DTC request Address Vector Transfer Data Transfer Transfer Data Transfer read information transfer information information transfer information read write read write Figure 7.13 DTC Operation Timing (Example of Short Address Mode in Chain Transfer) Clock DTC activation request...
Page 265: Number Of Dtc Execution Cycles
Section 7 Data Transfer Controller (DTC) 7.5.9 Number of DTC Execution Cycles Table 7.9 shows the execution status for a single DTC data transfer, and table 7.10 shows the number of cycles required for each execution. Table 7.9 DTC Execution Status Transfer Transfer Vector...
Page 266: Dtc Bus Release Timing
Section 7 Data Transfer Controller (DTC) Table 7.10 Number of Cycles Required for Each Execution State Chip Chip On-Chip I/O Object to be Accessed Registers External Devices Bus width Access cycles    Vector read S 12 + 4m 6 + 2m Execu- tion...
Page 267: Dtc Activation By Interrupt
Section 7 Data Transfer Controller (DTC) DTC Activation by Interrupt The procedure for using the DTC with interrupt activation is shown in figure 7.15. DTC activation by interrupt Clearing the RRS bit in DTCCR to 0 clears the read skip flag of transfer information.
Page 268: Examples Of Use Of The Dtc
Section 7 Data Transfer Controller (DTC) Examples of Use of the DTC 7.7.1 Normal Transfer Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal transfer mode (MD1 = MD0 = 0), and byte size (Sz1 = Sz0 = 0).
Page 269: Chain Transfer
Section 7 Data Transfer Controller (DTC) 7.7.2 Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating.
Page 270: Chain Transfer When Counter = 0
Section 7 Data Transfer Controller (DTC) 7.7.3 Chain Transfer when Counter = 0 By executing a second data transfer and performing re-setting of the first data transfer only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-kbyte input buffer is configured.
Page 271: Interrupt Sources
Section 7 Data Transfer Controller (DTC) Input circuit Transfer information located on the on-chip memory Input buffer 1st data transfer Chain transfer information (counter = 0) 2nd data transfer information Upper 8 bits of DAR Figure 7.16 Chain Transfer when Counter = 0 Interrupt Sources An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers or a data transfer for which the DISEL bit was set to 1.
Page 272: On-Chip Ram
Section 7 Data Transfer Controller (DTC) 7.9.2 On-Chip RAM Transfer information can be located in on-chip RAM. In this case, the RAME bit in SYSCR must not be cleared to 0. 7.9.3 DTCE Bit Setting For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are disabled, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register.
Page 273: Section 8 I/O Ports
Section 8 I/O Ports Section 8 I/O Ports Table 8.1 summarizes the port functions. The pins of each port also have other functions such as input/output pins of on-chip peripheral modules or external interrupt input pins. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, a port register (PORT) used to read the pin states, and an input buffer control register (ICR) that controls input buffer on/off.
Page 274 Section 8 I/O Ports Function Input Open- Schmitt- Pull-up Drain Trigger Output Port Description Input Output Input * Function Function  Port 2 General I/O port P27/ TIOCA5 All input also functioning TIOCB5 functions as interrupt inputs,  P26/ PO6/TMO1/ All input PPG outputs, TPU TIOCA5...
Page 275 Section 8 I/O Ports Function Input Open- Schmitt- Pull-up Drain Trigger Output Port Description Input Output Input* Function Function   Port 3 General I/O port P37/ TIOCA2/ PO15 All input also functioning TIOCB2 TCLKD-A functions as PPG outputs  P36/ PO14 All input...
Page 276 Section 8 I/O Ports Function Input Open- Schmitt- Pull-up Drain Trigger Output Port Description Input Output Input* Function Function       Port 6 General I/O port also functioning     as TMR I/Os, SCI ...
Page 277 Section 8 I/O Ports Function Input Open- Schmitt- Pull-up Drain Trigger Output Port Description Input Output Input* Function Function       Port B General I/O port also functioning    as bus control   ...
Page 278 Section 8 I/O Ports Function Input Open- Schmitt- Pull-up Drain Trigger Output Port Description Input Output Input* Function Function   Port F General I/O port A23/CS4-C/ CS5-C/ also functioning CS6-C/ as address CS7-C outputs  A22/CS6-D  A21/CS5-D  ...
Page 279: Register Descriptions
Section 8 I/O Ports Register Descriptions Table 8.2 lists each port registers. Table 8.2 Register Configuration in Each Port Registers Number of Port Pins PORT   Port 1  Port 2   Port 3     Port 5 ...
Page 280: Data Direction Register (Pnddr) (N = 1 To 3, 6, A, B, D To F, H, And I)
Section 8 I/O Ports 8.1.1 Data Direction Register (PnDDR) (n = 1 to 3, 6, A, B, D to F, H, and I) DDR is an 8-bit write-only register that specifies the port input or output for each bit. A read from the DDR is invalid and DDR is always read as an undefined value.
Page 281: Data Register (Pndr) (N = 1 To 3, 6, A, B, D To F, H, And I)
Section 8 I/O Ports 8.1.2 Data Register (PnDR) (n = 1 to 3, 6, A, B, D to F, H, and I) DR is an 8-bit readable/writable register that stores the output data of the pins to be used as the general output port.
Page 282: Input Buffer Control Register (Pnicr) (N = 1 To 3, 5, 6, A, B, D To F, H, And I)
Section 8 I/O Ports 8.1.4 Input Buffer Control Register (PnICR) (n = 1 to 3, 5, 6, A, B, D to F, H, and I) ICR is an 8-bit readable/writable register that controls the port input buffers. For bits in ICR set to 1, the input buffers of the corresponding pins are valid. For bits in ICR cleared to 0, the input buffers of the corresponding pins are invalid and the input signals are fixed high.
Page 283: Pull-Up Mos Control Register (Pnpcr) (N = D To F, H, And I)
Section 8 I/O Ports 8.1.5 Pull-Up MOS Control Register (PnPCR) (n = D to F, H, and I) PCR is an 8-bit readable/writable register that controls on/off of the port input pull-up MOS. If a bit in PCR is set to 1 while the pin is in input state, the input pull-up MOS corresponding to the bit in PCR is turned on.
Page 284: Open-Drain Control Register (Pnodr) (N = 2 And F)
Section 8 I/O Ports 8.1.6 Open-Drain Control Register (PnODR) (n = 2 and F) ODR is an 8-bit readable/writable register that selects the open-drain output function. If a bit in ODR is set to 1, the pin corresponding to that bit in ODR functions as an NMOS open- drain output.
Page 285 Section 8 I/O Ports P16/IRQ6-A/TCLKC-B The pin function is switched as shown below according to the P16DDR bit setting. Setting I/O Port Module Name Pin Function P16DDR I/O port P16 output P16 input (initial setting) 0 P15/IRQ5-A/TCLKB-B The pin function is switched as shown below according to the P15DDR bit setting. Setting I/O Port Module Name...
Page 286 Section 8 I/O Ports P13/ADTRG0/IRQ3-A The pin function is switched as shown below according to the P13DDR bit setting. Setting I/O Port Module Name Pin Function P13DDR I/O port P13 output P13 input (initial setting) 0 P12/SCK2/IRQ2-A The pin function is switched as shown below according to the combination of the SCI register setting and P12DDR bit setting.
Page 287: Port 2
Section 8 I/O Ports P10/TxD2/IRQ0-A The pin function is switched as shown below according to the combination of the SCI register setting and P10DDR bit setting. Setting I/O Port Module Name Pin Function TxD2_OE P10DDR  TxD2 output I/O port P10 output P10 input (initial setting) 0 8.2.2...
Page 288 Section 8 I/O Ports P26/PO6/TIOCA5/TMO1/TxD1 The pin function is switched as shown below according to the combination of the TPU, TMR, SCI, and PPG register settings and P26DDR bit setting. Setting I/O Port Module Name Pin Function TIOCA5_OE TMO1_OE TxD1_OE PO6_OE P26DDR ...
Page 289 Section 8 I/O Ports P24/PO4/TIOCA4/TIOCB4/TMRI1/SCK1 The pin function is switched as shown below according to the combination of the TPU, SCI, and PPG register settings and P24DDR bit setting. Setting I/O Port Module Name Pin Function TIOCB4_OE SCK1_OE PO4_OE P24DDR ...
Page 290 Section 8 I/O Ports P22 /PO2/TIOCC3/TMO0/TxD0/IRQ10-A The pin function is switched as shown below according to the combination of the TPU, TMR, SCI, and PPG register settings and P22DDR bit setting. Setting I/O Port Module Name Pin Function TIOCC3_OE TMO0_OE TxD0_OE PO2_OE P22DDR...
Page 291: Port 3
Section 8 I/O Ports P20/PO0/TIOCA3/TIOCB3/TMRI0/SCK0/IRQ8-A The pin function is switched as shown below according to the combination of the TPU, SCI, and PPG register settings and P20DDR bit setting. Setting I/O Port Module Name Pin Function TIOCB3_OE SCK0_OE PO0_OE P20DDR ...
Page 292 Section 8 I/O Ports P36/PO14/TIOCA2 The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P36DDR bit setting. Setting I/O Port Module Name Pin Function TIOCA2_OE PO14_OE P36DDR   TIOCA2 output ...
Page 293 Section 8 I/O Ports P34/PO12/TIOCA1 The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P34DDR bit setting. Setting I/O Port Module Name Pin Function TIOCA1_OE PO12_OE P34DDR   TIOCA1 output ...
Page 294 Section 8 I/O Ports P32/PO10/TIOCC0/TCLKA-A The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P32DDR bit setting. Setting I/O Port Module Name Pin Function TIOCC0_OE PO10_OE P32DDR   TIOCC0 output ...
Page 295: Port 5
Section 8 I/O Ports P30/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P30DDR bit setting. Setting I/O Port Module Name Pin Function TIOCA0_OE PO8_OE P30DDR   TIOCA0 output ...
Page 296: Port 6
Section 8 I/O Ports 8.2.5 Port 6 P65/TMO3 The pin function is switched as shown below according to the combination of the TMR register setting and P65DDR bit setting. Setting I/O Port Module Name Pin Function TMO3_OE P65DDR  TMO3 output I/O port P65 output P65 input...
Page 297 Section 8 I/O Ports P62/TMO2/SCK4/IRQ10-B The pin function is switched as shown below according to the combination of the TMR and SCI register settings and P62DDR bit setting. Setting I/O Port Module Name Pin Function TMO2_OE SCK4_OE P62DDR   TMO2 output ...
Page 298: Port A
Section 8 I/O Ports 8.2.6 Port A PA7/Bφ The pin function is switched as shown below according to the PA7DDR bit setting. Setting I/O Port Module Name Pin Function PA7DDR I/O port Bφ output* (initial setting) PA7 input The type of φ to be output switches according to the POSEL1 bit in SCKCR. For details, Note: see section 17.1.1, System Clock Control Register (SCKCR).
Page 299 Section 8 I/O Ports PA5/RD The pin function is always RD output. Setting MCU Operating Mode I/O Port Module Name Pin Function EXPE PA5DDR RD output  Bus controller (initial setting) PA4/LHWR/LUB The pin function is switched as shown below according to the combination of bus controller register, port function control register (PFCR), and the PA4DDR bit settings.
Page 300 Section 8 I/O Ports PA3/LLWR/LLB The pin function is switched as shown below according to the combination of bus controller register, and the PA3DDR bit settings. Setting Bus Controller I/O Port LLB_OE* LLWR_OE* Module Name Pin Function PA3DDR LLB output ...
Page 301 Section 8 I/O Ports PA1/BACK/(RD/WR) The pin function is switched as shown below according to the combination of bus controller register, port function control register (PFCR), and the PA1DDR bit settings. Setting Bus Controller I/O Port Byte control SRAM BACK_OE Module Name Pin Function Selection...
Page 302: Port B
Section 8 I/O Ports 8.2.7 Port B PB3/CS3/CS7-A The pin function is switched as shown below according to the combination of port function control register (PFCR) and the PB3DDR bit settings. Setting I/O Port CS3_OE CS7A_OE Module Name Pin Function PB3DDR CS3 output ...
Page 303 Section 8 I/O Ports PB1/CS1/CS2-B/CS5-A/CS6-B/CS7-B The pin function is switched as shown below according to the combination of port function control register (PFCR) and the PB1DDR bit settings. Setting I/O Port CS1_OE CS2B_OE CS5A_OE CS6B_OE CS7B_OE PB1DDR Module Name Pin Function CS1 output ...
Page 304: Port D
Section 8 I/O Ports 8.2.8 Port D PD7/A7, PD6/A6, PD5/A5, PD4/A4, PD3/A3, PD2/A2, PD1/A1, PD0/A0 The pin function is always address output. Setting I/O Port Module Name Pin Function PDnDDR Address output  Bus controller [Legend] n = 0 to 7 8.2.9 Port E PE7/A15, PE6/A14, PE5/A13, PE4/A12, PE3/A11, PE2/A10, PE1/A9, PE0/A8...
Page 305: Port F
Section 8 I/O Ports 8.2.10 Port F PF7/A23/CS4-C/CS5-C/CS6-C/CS7-C The pin function is switched as shown below according to the combination of port function control register (PFCR) and the PF7DDR bit settings. Setting I/O Port CS4-C CS5-C CS6-C CS7-C Module Name Pin Function A23_OE output...
Page 306 Section 8 I/O Ports PF5/A21/CS5-D The pin function is switched as shown below according to the combination of port function control register (PFCR) and the PF5DDR bit settings. Setting I/O Port CS5D_OE Module Name Pin Function A21_OE PF5DDR   Bus controller A21 output CS5-D output...
Page 307 Section 8 I/O Ports PF2/A18 The pin function is always address output. Setting I/O Port Module Name Pin Function PF2DDR  Bus controller A18 output PF1/A17 The pin function is always address output. Setting I/O Port Module Name Pin Function PF1DDR ...
Page 308: Port H
Section 8 I/O Ports 8.2.11 Port H PH7/D7, PH6/D6, PH5/D5, PH4/D4, PH3/D3, PH2/D2, PH1/D1, PH0/D0 The pin function is always data input/output. Setting I/O Port Module Name Pin Function PHnDDR  Bus controller Data I/O (initial setting) 8.2.12 Port I PI7/D15, PI6/D14, PI5/D13, PI4/D12, PI3/D11, PI2/D10, PI1/D9, PI0/D8 The pin function is switched as shown below according to the combination of operating mode, bus mode, and the PInDDR bit settings.
Page 309 Section 8 I/O Ports Table 8.5 Available Output Signals and Settings in Each Port Output Output Specification Signal Signal Selection Port Signal Name Name Register Settings Peripheral Module Settings SCK2_OE SCK2 When SCMR.SMIF = 1: SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0, SCR.CKE [1, 0] = 01 or while SMR.GM = 1 When SCMR.SMIF = 0: SCR.TE = 1 or SCR.RE = 1...
Page 310 Section 8 I/O Ports Output Output Specification Signal Signal Selection Port Signal Name Name Register Settings Peripheral Module Settings TIOCC3_OE TIOCC3 TPU.TMDR.BFA = 0, TPU.TIORL3.IOC3 = 0, TPU.TIORL3.IOD[1,0] = 01/10/11 TMO0_OE TMO0 TCSR.OS[3,2] = 01/10/11 or TCSR.OS[1,0] = 01/10/11 TxD0_OE TxD0 SCR.TE = 1 PO2_OE...
Page 311 Section 8 I/O Ports Output Output Specification Signal Signal Selection Port Signal Name Name Register Settings Peripheral Module Settings TIOCB0_OE TIOCB0 TPU.TIORH0.IOB3 = 0, TPU.TIORH0.IOB[1,0] = 01/10/11 PO9_OE NDERH.NDER9 = 1 TIOCA0_OE TIOCA0 TPU.TIORH0.IOA3 = 0, TPU.TIORH0.IOA[1,0] = 01/10/11 PO8_OE NDERH.NDER8 = 1 TMO3_OE TMO3...
Page 312 Section 8 I/O Ports Output Output Specification Signal Signal Selection Port Signal Name Name Register Settings Peripheral Module Settings CS3_OE PFCR0.CS3E = 1 CS7A_OE PFCR1.CS7S[A,B] = 00 PFCR0.CS7E = 1 CS2A_OE PFCR2.CS2S = 0 PFCR0.CS2E = 1 CS6A_OE PFCR1.CS6S[A,B] = 00 PFCR0.CS6E = 1 CS1_OE PFCR0.CS1E = 1...
Page 313 Section 8 I/O Ports Output Output Specification Signal Signal Selection Port Signal Name Name Register Settings Peripheral Module Settings A23_OE PFCR4.A23E = 1 CS4C_OE PFCR1.CS4S[A,B] = 10 PFCR0.CS4E = 1 CS5C_OE PFCR1.CS5S[A,B] = 10 PFCR0.CS5E = 1 CS6C_OE PFCR1.CS6S[A,B] = 10 PFCR0.CS6E = 1 CS7C_OE PFCR1.CS7S[A,B] = 10...
Page 314: Port Function Controller
Section 8 I/O Ports Port Function Controller The port function controller controls the I/O ports. The port function controller incorporates the following registers. • Port function control register 0 (PFCR0) • Port function control register 1 (PFCR1) • Port function control register 2 (PFCR2) •...
Page 315: Port Function Control Register 1 (Pfcr1)
Section 8 I/O Ports 8.3.2 Port Function Control Register 1 (PFCR1) PFCR1 selects the CS output pins. Bit Name CS7SA CS7SB CS6SA CS6SB CS5SA CS5SB CS4SA CS4SB Initial Value Initial Bit Name Value Description CS7 Output Pin Select CS7SA* Selects the output pin for CS7 when CS7 output is CS7SB* enabled (CS7E = 1) 00: Specifies pin PB3 as CS7-A output...
Page 316: Port Function Control Register 2 (Pfcr2)
Section 8 I/O Ports Initial Bit Name Value Description CS4 Output Pin Select CS4SA* Selects the output pin for CS4 when CS4 output is CS4SB* enabled (CS4E = 1) 00: Specifies pin PB0 as CS4-A output 01: Setting prohibited 10: Specifies pin PF7 as CS4-C output 11: Setting prohibited If multiple CS outputs are specified to a single pin according to the CSn output pin Note:...
Page 317 Section 8 I/O Ports Initial Bit Name Value Description BS Output Enable Enables/disables the BS output 0: Disables the BS output 1: Enables the BS output  Reserved This bit is always read as 0. The write value should always be 0. RDWRE* RD/WR Output Enable Enables/disables the RD/WR output...
Page 318: Port Function Control Register 4 (Pfcr4)
Section 8 I/O Ports 8.3.4 Port Function Control Register 4 (PFCR4) PFCR4 enables/disables the address output.      Bit Name A23E A22E A21E Initial Value Initial Bit Name Value Description A23E Address A23 Enable Enables/disables the address output (A23) 0: Disables the A23 output 1: Enables the A23 output A22E...
Page 319: Port Function Control Register 6 (Pfcr6)
Section 8 I/O Ports 8.3.5 Port Function Control Register 6 (PFCR6) PFCR6 selects the TPU clock input pin.       Bit Name LHWROE TCLKS Initial Value Initial Bit Name Value Description  Reserved This bit is always read as 1. The write value should always be 1.
Page 320: Port Function Control Register 9 (Pfcr9)
Section 8 I/O Ports 8.3.6 Port Function Control Register 9 (PFCR9) PFCR9 selects the multiple functions for the TPU I/O pins. Bit Name TPUMS5 TPUMS4 TPUMS3A TPUMS3B TPUMS2 TPUMS1 TPUMS0A TPUMS0B Initial Value Initial Bit Name Value Description TPUMS5 TPU I/O Pin Multiplex Function Select Selects TIOCA5 function 0: Specifies pin P26 as output compare output and input capture...
Page 321 Section 8 I/O Ports Initial Bit Name Value Description TPUMS2 TPU I/O Pin Multiplex Function Select Selects TIOCA2 function 0: Specifies P36 as output compare output and input capture 1: Specifies P37 as input capture input and P36 as output compare TPUMS1 TPU I/O Pin Multiplex Function Select...
Page 322: Port Function Control Register B (Pfcrb)
Section 8 I/O Ports 8.3.7 Port Function Control Register B (PFCRB) PFCRB selects the input pins for IRQ11 to IRQ8.     Bit Name ITS11 ITS10 ITS9 ITS8 Initial Value Initial Bit Name Value Description  7 to 4 All 0 Reserved These bits are always read as 0.
Page 323: Port Function Control Register C (Pfcrc)
Section 8 I/O Ports 8.3.8 Port Function Control Register C (PFCRC) PFCRC selects input pins for IRQ7 to IRQ0. Bit Name ITS7 ITS6 ITS5 ITS4 ITS3 ITS2 ITS1 ITS0 Initial Value Initial Bit Name Value Description IRQ7 Pin Select ITS7 Selects an input pin for IRQ7.
Page 324 Section 8 I/O Ports Initial Bit Name Value Description IRQ2 Pin Select ITS2 Selects an input pin for IRQ2. 0: Selects pin P12 as IRQ2-A input 1: Selects pin P52 as IRQ2-B output IRQ1 Pin Select ITS1 Selects an input pin for IRQ1. 0: Selects pin P11 as IRQ1-A input 1: Selects pin P51 as IRQ1-B output IRQ0 Pin Select...
Page 325: Usage Notes
Section 8 I/O Ports Usage Notes 8.4.1 Notes on Input Buffer Control Register (ICR) Setting • When changing the ICR setting, the LSI may malfunction due to an edge that is internally generated according to the pin states. To change the ICR setting, fix the pin high or disable the input function by setting the peripheral module allocated to the corresponding pin.
Page 326 Section 8 I/O Ports Rev.2.00 Jun. 28, 2007 Page 304 of 666 REJ09B0311-0200...
Page 327: Section 9 16-Bit Timer Pulse Unit (Tpu)
Section 9 16-Bit Timer Pulse Unit (TPU) Section 9 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. Tables 9.1 lists the 16-bit timer unit functions and figure 9.1 is a block diagram. Features •...
Page 328 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.1 TPU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Count clock Pφ/1 Pφ/1 Pφ/1 Pφ/1 Pφ/1 Pφ/1 Pφ/4 Pφ/4 Pφ/4 Pφ/4 Pφ/4 Pφ/4 Pφ/16 Pφ/16 Pφ/16 Pφ/16 Pφ/16...
Page 329 Section 9 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 A/D converter trigger TGRA_0 TGRA_1 TGRA_2 TGRA_3 TGRA_4 TGRA_5 compare compare compare compare compare compare match or match or match or match or match or match or...
Page 330 Section 9 16-Bit Timer Pulse Unit (TPU) Interrupt request signals Channel 3: TGI3A Input/output pins TGI3B Channel 3: TIOCA3 TGI3C TIOCB3 TGI3D TIOCC3 TCI3V TIOCD3 Channel 4: TGI4A Channel 4: TIOCA4 TGI4B TIOCB4 TCI4V Channel 5: TIOCA5 TCI4U TIOCB5 Channel 5: TGI5A TGI5B TCI5V...
Page 331: Input/Output Pins
Section 9 16-Bit Timer Pulse Unit (TPU) Input/Output Pins Table 9.3 shows TPU pin configurations. Table 9.2 Pin Configuration Channel Symbol Function TCLKA Input External clock A input pin (Channel 1 and 5 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 and 5 phase counting mode B phase input) TCLKC...
Page 332: Register Descriptions
Section 9 16-Bit Timer Pulse Unit (TPU) Register Descriptions The TPU has the following registers in each channel. • Channel 0  Timer control register_0 (TCR_0)  Timer mode register_0 (TMDR_0)  Timer I/O control register H_0 (TIORH_0)  Timer I/O control register L_0 (TIORL_0) ...
Page 333 Section 9 16-Bit Timer Pulse Unit (TPU) • Channel 3  Timer control register_3 (TCR_3)  Timer mode register_3 (TMDR_3)  Timer I/O control register H_3 (TIORH_3)  Timer I/O control register L_3 (TIORL_3)  Timer interrupt enable register_3 (TIER_3) ...
Page 334: Timer Control Register (Tcr)
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.1 Timer Control Register (TCR) TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only while TCNT operation is stopped. Bit Name CCLR2 CCLR1...
Page 335 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.3 CCLR2 to CCLR0 (Channels 0 and 3) Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description 0, 3 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/...
Page 336 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) Bit 7 Reserved Bit 6 Bit 5 Channel CCLR1 CCLR0 Description 1, 2, 4, 5 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture...
Page 337 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.6 TPSC2 to TPSC0 (Channel 0) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input...
Page 338 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.8 TPSC2 to TPSC0 (Channel 2) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input...
Page 339 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.10 TPSC2 to TPSC0 (Channel 4) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on Pφ/1 Internal clock: counts on Pφ/4 Internal clock: counts on Pφ/16 Internal clock: counts on Pφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input...
Page 340: Timer Mode Register (Tmdr)
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.2 Timer Mode Register (TMDR) TMDR sets the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only while TCNT operation is stopped. Bit Name Initial Value Initial...
Page 341: Timer I/O Control Register (Tior)
Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.12 MD3 to MD0 Bit 3 Bit 2 Bit 1 Bit 0 MD3* MD2* Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 ...
Page 342 Section 9 16-Bit Timer Pulse Unit (TPU) • TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Bit Name IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial Value • TIORL_0, TORL_3 Bit Name IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial Value •...
Page 343 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.13 TIORH_0 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_0 IOB3 IOB2 IOB1 IOB0 Function TIOCB0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 344 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.14 TIORL_0 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRD_0 IOD3 IOD2 IOD1 IOD0 Function TIOCD0 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 345 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.15 TIOR_1 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_1 IOB3 IOB2 IOB1 IOB0 Function TIOCB1 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 346 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.16 TIOR_2 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_2 IOB3 IOB2 IOB1 IOB0 Function TIOCB2 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 347 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.17 TIORH_3 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_3 IOB3 IOB2 IOB1 IOB0 Function TIOCB3 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 348 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.18 TIORL_3 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRD_3 IOD3 IOD2 IOD1 IOD0 Function TIOCD3 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 349 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.19 TIOR_4 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_4 IOB3 IOB2 IOB1 IOB0 Function TIOCB4 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 350 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.20 TIOR_5 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_5 IOB3 IOB2 IOB1 IOB0 Function TIOCB5 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 351 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.21 TIORH_0 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_0 IOA3 IOA2 IOA1 IOA0 Function TIOCA0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 352 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.22 TIORL_0 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRC_0 IOC3 IOC2 IOC1 IOC0 Function TIOCC0 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 353 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.23 TIOR_1 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_1 IOA3 IOA2 IOA1 IOA0 Function TIOCA1 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 354 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.24 TIOR_2 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_2 IOA3 IOA2 IOA1 IOA0 Function TIOCA2 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 355 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.25 TIORH_3 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_3 IOA3 IOA2 IOA1 IOA0 Function TIOCA3 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 356 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.26 TIORL_3 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRC_3 IOC3 IOC2 IOC1 IOC0 Function TIOCC3 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 357 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.27 TIOR_4 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_4 IOA3 IOA2 IOA1 IOA0 Function TIOCA4 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 358 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.28 TIOR_5 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_5 IOA3 IOA2 IOA1 IOA0 Function TIOCA5 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output...
Page 359: Timer Interrupt Enable Register (Tier)
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.4 Timer Interrupt Enable Register (TIER) TIER controls enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Name TTGE TCIEU TCIEV TGIED TCIEC TGIEB TGIEA...
Page 360 Section 9 16-Bit Timer Pulse Unit (TPU) Initial Bit Name value Description TGIED TGR Interrupt Enable D Enables/disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved.
Page 361: Timer Status Register (Tsr)
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.5 Timer Status Register (TSR) TSR indicates the status of each channel. The TPU has six TSR registers, one for each channel. Bit Name TCFD TCFU TCFV TGFD TGFC TGFB TGFA Initial Value R/(W)* R/(W)* R/(W)*...
Page 362 Section 9 16-Bit Timer Pulse Unit (TPU) Initial Bit Name value Description TCFV R/(W)* Overflow Flag Status flag that indicates that a TCNT overflow has occurred. [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) [Clearing condition] When a 0 is written to TCFV after reading TCFV = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to...
Page 363 Section 9 16-Bit Timer Pulse Unit (TPU) Initial Bit Name value Description TGFC R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
Page 364 Section 9 16-Bit Timer Pulse Unit (TPU) Initial Bit Name value Description TGFA R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions] • When TCNT = TGRA while TGRA is functioning as output compare register •...
Page 365: Timer Counter (Tcnt)
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.6 Timer Counter (TCNT) TCNT is a 16-bit readable/writable counter. The TPU has six TCNT counters, one for each channel. TCNT is initialized to H'0000 by a reset or in hardware standby mode. TCNT cannot be accessed in 8-bit units.
Page 366: Timer Start Register (Tstr)
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.8 Timer Start Register (TSTR) TSTR starts or stops operation for channels 0 to 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit Name CST5 CST4...
Page 367: Timer Synchronous Register (Tsyr)
Section 9 16-Bit Timer Pulse Unit (TPU) 9.3.9 Timer Synchronous Register (TSYR) TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Name SYNC5 SYNC4...
Page 368: Operation
Section 9 16-Bit Timer Pulse Unit (TPU) Operation 9.4.1 Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting.
Page 369 Section 9 16-Bit Timer Pulse Unit (TPU) (b) Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter.
Page 370 Section 9 16-Bit Timer Pulse Unit (TPU) Figure 9.4 illustrates periodic counter operation. TCNT value Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software or DTC activation Figure 9.4 Periodic Counter Operation Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match.
Page 371 Section 9 16-Bit Timer Pulse Unit (TPU) (b) Examples of waveform output operation Figure 9.6 shows an example of 0-output and 1-output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change.
Page 372 Section 9 16-Bit Timer Pulse Unit (TPU) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source.
Page 373 Section 9 16-Bit Timer Pulse Unit (TPU) (b) Example of input capture operation Figure 9.9 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 374: Synchronous Operation
Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR. Synchronous operation enables TGR to be incremented with respect to a single time base.
Page 375 Section 9 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation Figure 9.11 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Page 376: Buffer Operation
Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or a compare match register.
Page 377 Section 9 16-Bit Timer Pulse Unit (TPU) • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in TGR is transferred to the buffer register. This operation is illustrated in figure 9.13.
Page 378 Section 9 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation When TGR is an output compare register Figure 9.15 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Page 379: Cascaded Operation
Section 9 16-Bit Timer Pulse Unit (TPU) TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA H'0532 H'0F07 H'09FB TGRA H'0532 H'0F07 TGRC Figure 9.16 Example of Buffer Operation (2) 9.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter.
Page 380 Section 9 16-Bit Timer Pulse Unit (TPU) Example of Cascaded Operation Setting Procedure Figure 9.17 shows an example of the setting procedure for cascaded operation. Set bits TPSC2 to TPSC0 in the channel 1 Cascaded operation (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting.
Page 381: Pwm Modes
Section 9 16-Bit Timer Pulse Unit (TPU) Figure 9.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. TCLKC TCLKD TCNT_2...
Page 382 Section 9 16-Bit Timer Pulse Unit (TPU) 2. PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a cycle register compare match, the output value of each pin is the initial value set in TIOR.
Page 383 Section 9 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure Figure 9.20 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
Page 384 Section 9 16-Bit Timer Pulse Unit (TPU) TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 9.21 Example of PWM Mode Operation (1) Figure 9.22 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform.
Page 385 Section 9 16-Bit Timer Pulse Unit (TPU) Figure 9.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB changed TGRA TGRB TGRB changed TGRB changed H'0000 Time TIOCA 0% duty TCNT value Output does not change when compare matches in cycle register and duty register occur simultaneously...
Page 386: Phase Counting Mode
Section 9 16-Bit Timer Pulse Unit (TPU) 9.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Page 387 Section 9 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. Phase counting mode 1 Figure 9.25 shows an example of phase counting mode 1 operation, and table 9.33 summarizes the TCNT up/down-count conditions.
Page 388 Section 9 16-Bit Timer Pulse Unit (TPU) (b) Phase counting mode 2 Figure 9.26 shows an example of phase counting mode 2 operation, and table 9.34 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value...
Page 389 Section 9 16-Bit Timer Pulse Unit (TPU) Phase counting mode 3 Figure 9.27 shows an example of phase counting mode 3 operation, and table 9.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value...
Page 390 Section 9 16-Bit Timer Pulse Unit (TPU) (d) Phase counting mode 4 Figure 9.28 shows an example of phase counting mode 4 operation, and table 9.36 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value...
Page 391 Section 9 16-Bit Timer Pulse Unit (TPU) Phase Counting Mode Application Example Figure 9.29 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed.
Page 392: Interrupt Sources
Section 9 16-Bit Timer Pulse Unit (TPU) Interrupt Sources There are three kinds of TPU interrupt sources: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
Page 393 Section 9 16-Bit Timer Pulse Unit (TPU) Channel Name Interrupt Source Interrupt Flag DTC Activation TGI2A TGRA_2 input TGFA_2 Possible capture/compare match TGI2B TGRB_2 input TGFB_2 Possible capture/compare match TCI2V TCNT_2 overflow TCFV_2 Not possible TCI2U TCNT_2 underflow TCFU_2 Not possible TGI3A TGRA_3 input TGFA_3...
Page 394: Dtc Activation
Section 9 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a channel. The interrupt request is cleared by clearing the TGF flag to 0.
Page 395: Operation Timing
Section 9 16-Bit Timer Pulse Unit (TPU) Operation Timing 9.8.1 Input/Output Timing TCNT Count Timing Figure 9.30 shows TCNT count timing in internal clock operation, and figure 9.31 shows TCNT count timing in external clock operation. Falling edge Rising edge Falling edge Internal clock TCNT input clock...
Page 396 Section 9 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin).
Page 397 Section 9 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture Figure 9.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 9.35 shows the timing when counter clearing by input capture occurrence is specified. Compare match signal Counter clear...
Page 398 Section 9 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing Figures 9.36 and 9.37 show the timings in buffer operation. TCNT Compare match signal TGRA, TGRB TGRC, TGRD Figure 9.36 Buffer Operation Timing (Compare Match) Input capture signal TCNT TGRA, TGRB TGRC, TGRD...
Page 399: Interrupt Signal Timing
Section 9 16-Bit Timer Pulse Unit (TPU) 9.8.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 9.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. TCNT input clock TCNT...
Page 400 Section 9 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing Figure 9.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 9.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing.
Page 401 Section 9 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 9.42 shows the timing for status flag clearing by the CPU, and figures 9.43 and 9.44 show the timing for status flag clearing by the DTC.
Page 402 Section 9 16-Bit Timer Pulse Unit (TPU) read cycle write cycle Source Destination Address address address Status flag Period in which the next transfer request is masked Interrupt request signal Figure 9.43 Timing for Status Flag Clearing by DTC Activation (1) read cycle write cycle Address...
Page 403: Usage Notes
Section 9 16-Bit Timer Pulse Unit (TPU) Usage Notes 9.9.1 Module Stop State Setting Operation of the TPU can be disabled or enabled using the module stop control register. The initial setting is for operation of the TPU to be halted. Register access is enabled by clearing module stop state.
Page 404: Caution On Cycle Setting
Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: Counter frequency Operating frequency...
Page 405: Conflict Between Tcnt Write And Increment Operations
Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.5 Conflict between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 9.47 shows the timing in this case. TCNT write cycle Address TCNT address...
Page 406: Conflict Between Buffer Register Write And Compare Match
Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.7 Conflict between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the write data. Figure 9.49 shows the timing in this case.
Page 407: Conflict Between Tgr Write And Input Capture
Section 9 16-Bit Timer Pulse Unit (TPU) TGR read cycle Address TGR address Read Input capture signal Internal data bus Figure 9.50 Conflict between TGR Read and Input Capture 9.9.9 Conflict between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed.
Page 408: Conflict Between Buffer Register Write And Input Capture
Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.10 Conflict between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 9.52 shows the timing in this case.
Page 409: Conflict Between Overflow/Underflow And Counter Clearing
Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.11 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 9.53 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
Page 410: Multiplexing Of I/O Pins
Section 9 16-Bit Timer Pulse Unit (TPU) 9.9.13 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin.
Page 411: Section 10 Programmable Pulse Generator (Ppg)
Section 10 Programmable Pulse Generator (PPG) Section 10 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that can operate both simultaneously and independently.
Page 412 Section 10 Programmable Pulse Generator (PPG) Compare match signals NDERH NDERL Control logic PO15 PO14 Pulse output PO13 pins, group 3 PO12 Internal PODRH NDRH PO11 data bus PO10 Pulse output pins, group 2 Pulse output pins, group 1 PODRL NDRL Pulse output pins, group 0...
Page 413: Input/Output Pins
Section 10 Programmable Pulse Generator (PPG) 10.2 Input/Output Pins Table 10.1 shows the PPG pin configuration. Table 10.1 Pin Configuration Pin Name Function PO15 Output Group 3 pulse output PO14 Output PO13 Output PO12 Output PO11 Output Group 2 pulse output PO10 Output Output...
Page 414: Register Descriptions
Section 10 Programmable Pulse Generator (PPG) 10.3 Register Descriptions The PPG has the following registers. • Next data enable register H (NDERH) • Next data enable register L (NDERL) • Output data register H (PODRH) • Output data register L (PODRL) •...
Page 415 Section 10 Programmable Pulse Generator (PPG) • NDERH Initial Bit Name Value Description NDER15 Next Data Enable 15 to 8 NDER14 When a bit is set to 1, the value in the corresponding NDRH bit is transferred to the PODRH bit by the selected NDER13 output trigger.
Page 416: Output Data Registers H, L (Podrh, Podrl)
Section 10 Programmable Pulse Generator (PPG) 10.3.2 Output Data Registers H, L (PODRH, PODRL) PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified. •...
Page 417: Next Data Registers H, L (Ndrh, Ndrl)
Section 10 Programmable Pulse Generator (PPG) • PODRL Initial Bit Name Value Description POD7 Output Data Register 7 to 0 POD6 For bits which have been set to pulse output by NDERL, the output trigger transfers NDRL values to this register POD5 during PPG operation.
Page 418 Section 10 Programmable Pulse Generator (PPG) • NDRH If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Initial Bit Name Value Description...
Page 419 Section 10 Programmable Pulse Generator (PPG) • NDRL If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Initial Bit Name Value Description...
Page 420: Ppg Output Control Register (Pcr)
Section 10 Programmable Pulse Generator (PPG) 10.3.4 PPG Output Control Register (PCR) PCR selects output trigger signals on a group-by-group basis. For details on output trigger selection, refer to section 10.3.5, PPG Output Mode Register (PMR). G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1...
Page 421: Ppg Output Mode Register (Pmr)
Section 10 Programmable Pulse Generator (PPG) 10.3.5 PPG Output Mode Register (PMR) PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values at compare match A or B of the TPU that becomes the output trigger.
Page 422 Section 10 Programmable Pulse Generator (PPG) Initial Bit Name Value Description G3NOV Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) G2NOV...
Page 423: Operation
Section 10 Programmable Pulse Generator (PPG) 10.4 Operation Figure 10.2 shows a schematic diagram of the PPG. PPG pulse output is enabled when the corresponding bits in NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting.
Page 424: Sample Setup Procedure For Normal Pulse Output
Section 10 Programmable Pulse Generator (PPG) 10.4.2 Sample Setup Procedure for Normal Pulse Output Figure 10.4 shows a sample procedure for setting up normal pulse output. Set TIOR to make TGRA an output Normal PPG output compare register (with output disabled). Set the PPG output trigger cycle.
Page 425: Example Of Normal Pulse Output (Example Of 5-Phase Pulse Output)
Section 10 Programmable Pulse Generator (PPG) 10.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output) Figure 10.5 shows an example in which pulse output is used for cyclic 5-phase pulse output. TCNT value TCNT Compare match TGRA H'0000 Time NDRH PODRH...
Page 426: Non-Overlapping Pulse Output
Section 10 Programmable Pulse Generator (PPG) 1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set a cycle in TGRA so the counter will be cleared by compare match A. Set the TGIEA bit in TIER to 1 to enable the compare match/input capture A (TGIA) interrupt.
Page 427 Section 10 Programmable Pulse Generator (PPG) Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlapping margin).
Page 428: Sample Setup Procedure For Non-Overlapping Pulse Output
Section 10 Programmable Pulse Generator (PPG) 10.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output Figure 10.8 shows a sample procedure for setting up non-overlapping pulse output. Set TIOR to make TGRA and TGRB Non-overlapping output compare registers (with output pulse output disabled).
Page 429: Example Of Non-Overlapping Pulse Output (Example Of 4-Phase Complementary Non-Overlapping Pulse Output)
Section 10 Programmable Pulse Generator (PPG) 10.4.6 Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary Non-Overlapping Pulse Output) Figure 10.9 shows an example in which pulse output is used for 4-phase complementary non- overlapping pulse output. TCNT value TGRB TCNT TGRA H'0000...
Page 430 Section 10 Programmable Pulse Generator (PPG) 1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the cycle in TGRB and the non-overlapping margin in TGRA, and set the counter to be cleared by compare match B.
Page 431: Inverted Pulse Output
Section 10 Programmable Pulse Generator (PPG) 10.4.7 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 10.10 shows the outputs when the G3INV and G2INV bits are cleared to 0, in addition to the settings of figure 10.9.
Page 432: Pulse Output Triggered By Input Capture
Section 10 Programmable Pulse Generator (PPG) 10.4.8 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal.
Page 433: Section 11 8-Bit Timers (Tmr)
Section 11 8-Bit Timers (TMR) Section 11 8-Bit Timers (TMR) This LSI has two units (unit 0 and unit 1) of an on-chip 8-bit timer module that comprise two 8-bit counter channels, totaling four channels. The 8-bit timer module can be used to count external events and also be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with a desired duty cycle using a compare-match signal with two registers.
Page 434 Section 11 8-Bit Timers (TMR) Internal clocks P /2 P /8 P /32 P /64 P /1024 P /8192 External clocks Counter clock 1 Counter clock 0 TMCI0 Clock select TMCI1 TCORA_0 TCORA_1 Compare match A1 Compare match A0 Comparator A_0 Comparator A_1 Overflow 1 TMO0...
Page 435 Section 11 8-Bit Timers (TMR) Internal clocks P /2 P /8 P /32 P /64 P /1024 P /8192 Counter clock 3 External clocks Counter clock 2 TMCI2 Clock select TMCI3 TCORA_2 TCORA_3 Compare match A3 Compare match A2 Comparator A_3 Comparator A_3 Overflow 3 TMO2...
Page 436: Input/Output Pins
Section 11 8-Bit Timers (TMR) 11.2 Input/Output Pins Table 11.1 shows the pin configuration of the TMR. Table 11.1 Pin Configuration Unit Channel Name Symbol Function Timer output pin TMO0 Output Outputs compare match Timer clock input pin TMCI0 Input Inputs external clock for counter Timer reset input pin TMRI0...
Page 437: Register Descriptions
Section 11 8-Bit Timers (TMR) 11.3 Register Descriptions The TMR has the following registers. Unit 0: • Channel 0  Timer counter_0 (TCNT_0)  Time constant register A_0 (TCORA_0)  Time constant register B_0 (TCORB_0)  Timer control register_0 (TCR_0) ...
Page 438: Timer Counter (Tcnt)
Section 11 8-Bit Timers (TMR) 11.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR and bits ICKS1 and ICKS0 in TCCR are used to select a clock. TCNT can be cleared by an external reset input signal, compare match A signal, or compare match B signal.
Page 439: Time Constant Register B (Tcorb)
Section 11 8-Bit Timers (TMR) 11.3.3 Time Constant Register B (TCORB) TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding CMFB flag in TCSR is set to 1.
Page 440 Section 11 8-Bit Timers (TMR) Initial Bit Name Value Description CMIEA Compare Match Interrupt Enable A Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag in TCSR is set to 1. 0: CMFA interrupt requests (CMIA) are disabled 1: CMFA interrupt requests (CMIA) are enabled OVIE Timer Overflow Interrupt Enable...
Page 441: Timer Counter Control Register (Tccr)
Section 11 8-Bit Timers (TMR) 11.3.5 Timer Counter Control Register (TCCR) TCCR selects the TCNT internal clock source and controls external reset input. TMRIS ICKS1 ICKS0 Bit Name Initial Value Initial Bit Name Value Description  7 to 4 Reserved These bits are always read as 0.
Page 442 Section 11 8-Bit Timers (TMR) Table 11.2 Clock Input to TCNT and Count Condition TCCR Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description   TMR_0 Clock input prohibited. Uses internal clock. Counts at rising edge of Pφ/8. Uses internal clock.
Page 443: Timer Control/Status Register (Tcsr)
Section 11 8-Bit Timers (TMR) TCCR Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description   Uses external clock. Counts at rising edge*   Uses external clock. Counts at falling edge* ...
Page 444 Section 11 8-Bit Timers (TMR) • TCSR_0 Initial Bit Name Value Description CMFB R/(W)* Compare Match Flag B [Setting condition] • When TCNT matches TCORB [Clearing conditions] • When writing 0 after reading CMFB = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) •...
Page 445 Section 11 8-Bit Timers (TMR) Initial Bit Name Value Description Output Select 3 and 2* These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs. 00: No change when compare match B occurs 01: 0 is output when compare match B occurs 10: 1 is output when compare match B occurs 11: Output is inverted when compare match B occurs...
Page 446 Section 11 8-Bit Timers (TMR) Initial Bit Name Value Description CMFA R/(W)* Compare Match Flag A [Setting condition] When TCNT matches TCORA [Clearing conditions] • When writing 0 after reading CMFA = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) •...
Page 447: Operation
Section 11 8-Bit Timers (TMR) 11.4 Operation 11.4.1 Pulse Output Figure 11.3 shows an example of the 8-bit timer being used to generate a pulse output with a desired duty cycle. The control bits are set as follows: 1. In TCR, clear bit CCLR1 to 0 and set bit CCLR0 to 1 so that TCNT is cleared at a TCORA compare match.
Page 448: Reset Input
Section 11 8-Bit Timers (TMR) 11.4.2 Reset Input Figure 11.4 shows an example of the 8-bit timer being used to generate a pulse which is output after a desired delay time from a TMRI input. The control bits are set as follows: 1.
Page 449: Operation Timing
Section 11 8-Bit Timers (TMR) 11.5 Operation Timing 11.5.1 TCNT Count Timing Figure 11.5 shows the TCNT count timing for internal clock input. Figure 11.6 shows the TCNT count timing for external clock input. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges.
Page 450: Timing Of Timer Output At Compare Match
Section 11 8-Bit Timers (TMR) TCNT N + 1 TCOR Compare match signal Figure 11.7 Timing of CMF Setting at Compare Match 11.5.3 Timing of Timer Output at Compare Match When a compare match signal is generated, the timer output changes as specified by bits OS3 to OS0 in TCSR.
Page 451: Timing Of Tcnt External Reset
Section 11 8-Bit Timers (TMR) 11.5.5 Timing of TCNT External Reset TCNT is cleared at the rising edge or high level of an external reset input, depending on the settings of bits CCLR1 and CCLR0 in TCR. The clear pulse width must be at least 2 states. Figures 11.10 and 11.11 show the timing of this operation.
Page 452: Operation With Cascaded Connection
Section 11 8-Bit Timers (TMR) 11.6 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode).
Page 453: Interrupt Sources
Section 11 8-Bit Timers (TMR) 11.7 Interrupt Sources 11.7.1 Interrupt Sources and DTC Activation There are three interrupt sources for the 8-bit timer (TMR_0 or TMR_1): CMIA, CMIB, and OVI. Their interrupt sources and priorities are shown in table 11.3. Each interrupt source is enabled or disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the interrupt controller.
Page 454: Usage Notes
Section 11 8-Bit Timers (TMR) 11.8 Usage Notes 11.8.1 Notes on Setting Cycle If the compare match is selected for counter clear, TCNT is cleared at the last state in the cycle in which the values of TCNT and TCOR match. TCNT updates the counter value at this last state. Therefore, the counter frequency is obtained by the following formula.
Page 455: Conflict Between Tcnt Write And Increment
Section 11 8-Bit Timers (TMR) 11.8.3 Conflict between TCNT Write and Increment If a TCNT input clock pulse is generated during the T state of a TCNT write cycle, the write takes priority and the counter is not incremented as shown in figure 11.14. TCNT write cycle by CPU Address TCNT address...
Page 456: Conflict Between Compare Matches A And B
Section 11 8-Bit Timers (TMR) 11.8.5 Conflict between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 11.4.
Page 457 Section 11 8-Bit Timers (TMR) Table 11.5 Switching of Internal Clock and TCNT Operation Timing to Change CKS1 and CKS0 Bits TCNT Clock Operation Switching from low to low* Clock before switchover Clock after switchover TCNT input clock TCNT N + 1 CKS bits changed Switching from low to high* Clock before...
Page 458: Mode Setting With Cascaded Connection
Section 11 8-Bit Timers (TMR) 11.8.7 Mode Setting with Cascaded Connection If 16-bit counter mode and compare match count mode are specified at the same time, input clocks for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter mode and compare match count mode simultaneously.
Page 459: Section 12 Watchdog Timer (Wdt)
Section 12 Watchdog Timer (WDT) Section 12 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At the same time, the WDT can also generate an internal reset signal.
Page 460: Input/Output Pin
Section 12 Watchdog Timer (WDT) 12.2 Input/Output Pin Table 12.1 shows the WDT pin configuration. Table 12.1 Pin Configuration Name Symbol Function WDTOVF Watchdog timer overflow Output Outputs a counter overflow signal in watchdog timer mode 12.3 Register Descriptions The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers.
Page 461: Timer Control/Status Register (Tcsr)
Section 12 Watchdog Timer (WDT) 12.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode.   Bit Name WT/IT CKS2 CKS1 CKS0 Initial Value R/(W)* Note: * Only 0 can be written to this bit, to clear the flag. Initial Bit Name Value...
Page 462 Section 12 Watchdog Timer (WDT) Initial Bit Name Value Description Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00.  4, 3 All 1 Reserved These are read-only bits and cannot be modified.
Page 463: Reset Control/Status Register (Rstcsr)
Section 12 Watchdog Timer (WDT) 12.3.3 Reset Control/Status Register (RSTCSR) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by WDT overflows.
Page 464: Operation
Section 12 Watchdog Timer (WDT) 12.4 Operation 12.4.1 Watchdog Timer Mode To use the WDT in watchdog timer mode, set both the WT/IT and TME bits in TCSR to 1. During watchdog timer operation, if TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output.
Page 465 Section 12 Watchdog Timer (WDT) TCNT value Overflow H'FF Time H'00 WT/IT = 1 WOVF = 1 H'00 written WT/IT = 1 H'00 written TME = 1 to TCNT TME = 1 to TCNT WDTOVF and internal reset are generated WDTOVF signal 133 states * Internal reset signal *...
Page 466: Interval Timer Mode
Section 12 Watchdog Timer (WDT) 12.4.2 Interval Timer Mode To use the WDT as an interval timer, set the WT/IT bit to 0 and the TME bit to 1 in TCSR. When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows.
Page 467: Usage Notes
Section 12 Watchdog Timer (WDT) 12.6 Usage Notes 12.6.1 Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below.
Page 468: Conflict Between Timer Counter (Tcnt) Write And Increment
Section 12 Watchdog Timer (WDT) Reading from TCNT, TCSR, and RSTCSR These registers can be read from in the same way as other registers. For reading, TCSR is assigned to address H'FFA4, TCNT to address H'FFA5, and RSTCSR to address H'FFA7. 12.6.2 Conflict between Timer Counter (TCNT) Write and Increment If a TCNT clock pulse is generated during the T2 state of a TCNT write cycle, the write takes...
Page 469: Internal Reset In Watchdog Timer Mode
Section 12 Watchdog Timer (WDT) 12.6.5 Internal Reset in Watchdog Timer Mode This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer mode operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low.
Page 470 Section 12 Watchdog Timer (WDT) Rev.2.00 Jun. 28, 2007 Page 448 of 666 REJ09B0311-0200...
Page 471: Section 13 Serial Communication Interface (Sci)
Section 13 Serial Communication Interface (SCI) Section 13 Serial Communication Interface (SCI) This LSI has four independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Page 472 Section 13 Serial Communication Interface (SCI) • Average transfer rate generator (SCI_2 only) 10.667-MHz operation: 460.606 kbps or 115.152 kbps can be selected 16-MHz operation: 720 kbps, 460.784 kbps, or 115.196 kbps can be selected 32-MHz operation: 720 kbps Clocked Synchronous Mode: •...
Page 473: Input/Output Pins
Section 13 Serial Communication Interface (SCI) 13.2 Input/Output Pins Table 13.1 lists the pin configuration of the SCI. Table 13.1 Pin Configuration Channel Pin Name* Function SCK0 Channel 0 clock input/output RxD0 Input Channel 0 receive data input TxD0 Output Channel 0 transmit data output SCK1 Channel 1 clock input/output...
Page 474: Register Descriptions
Section 13 Serial Communication Interface (SCI) 13.3 Register Descriptions The SCI has the following registers. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modesnormal serial communication interface mode and smart card interface mode; therefore, the bits are described separately for each mode in the corresponding register sections.
Page 475 Section 13 Serial Communication Interface (SCI) Channel 2: • Receive shift register_2 (RSR_2) • Transmit shift register_2 (TSR_2) • Receive data register_2 (RDR_2) • Transmit data register_2 (TDR_2) • Serial mode register_2 (SMR_2) • Serial control register_2 (SCR_2) • Serial status register_2 (SSR_2) •...
Page 476: Receive Shift Register (Rsr)
Section 13 Serial Communication Interface (SCI) 13.3.1 Receive Shift Register (RSR) RSR is a shift register which is used to receive serial data input from the RxD pin and converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically.
Page 477: Transmit Shift Register (Tsr)
Section 13 Serial Communication Interface (SCI) 13.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first automatically transfers transmit data from TDR to TSR, and then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU.
Page 478 Section 13 Serial Communication Interface (SCI) Initial Bit Name Value Description Parity Enable (valid only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception.
Page 479 Section 13 Serial Communication Interface (SCI) Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Initial Bit Name Value Description GSM Mode Setting this bit to 1 allows GSM mode operation. In GSM mode, the TEND set timing is put forward to 11.0 etu from the start and the clock output control function is appended.
Page 480: Serial Control Register (Scr)
Section 13 Serial Communication Interface (SCI) Initial Bit Name Value Description CKS1 Clock Select 1,0 CKS0 These bits select the clock source for the baud rate generator. 00: Pφ clock (n = 0) 01: Pφ/4 clock (n = 1) 10: Pφ/16 clock (n = 2) 11: Pφ/64 clock (n = 3) For the relation between the settings of these bits and the baud rate, see section 13.3.9, Bit Rate Register...
Page 481 Section 13 Serial Communication Interface (SCI) Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Initial Bit Name Value Description Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled.
Page 482 Section 13 Serial Communication Interface (SCI) Initial Bit Name Value Description MPIE Multiprocessor Interrupt Enable (valid only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled.
Page 483 Section 13 Serial Communication Interface (SCI) Initial Bit Name Value Description CKE1 Clock Enable 1, 0 CKE0 These bits select the clock source and SCK pin function. • Asynchronous mode 00: On-chip baud rate generator (SCK pin functions as I/O port.) 01: On-chip baud rate generator (Outputs a clock with the same frequency as the bit rate from the SCK pin.)
Page 484 Section 13 Serial Communication Interface (SCI) Initial Bit Name Value Description Transmit Enable When this bit is set to 1, transmission is enabled. Under this condition, serial transmission is started by writing transmit data to TDR, and clearing the TDRE flag in SSR to 0.
Page 485: Serial Status Register (Ssr)
Section 13 Serial Communication Interface (SCI) 13.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode.
Page 486 Section 13 Serial Communication Interface (SCI) Initial Bit Name Value Description RDRF R/(W)* Receive Data Register Full Indicates whether receive data is stored in RDR. [Setting condition] • When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions] •...
Page 487 Section 13 Serial Communication Interface (SCI) Initial Bit Name Value Description R/(W)* Framing Error Indicates that a framing error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] • When the stop bit is 0 In 2-stop-bit mode, only the first stop bit is checked whether it is 1 but the second stop bit is not checked.
Page 488 Section 13 Serial Communication Interface (SCI) Initial Bit Name Value Description TEND Transmit End [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a transmit character [Clearing conditions] •...
Page 489 Section 13 Serial Communication Interface (SCI) Initial Bit Name Value Description RDRF R/(W)* Receive Data Register Full Indicates whether receive data is stored in RDR. [Setting condition] • When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions] •...
Page 490 Section 13 Serial Communication Interface (SCI) Initial Bit Name Value Description R/(W)* Error Signal Status [Setting condition] • When a low error signal is sampled [Clearing condition] • When 0 is written to ERS after reading ERS = 1 R/(W)* Parity Error Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally.
Page 491 Section 13 Serial Communication Interface (SCI) Initial Bit Name Value Description TEND Transmit End This bit is set to 1 when no error signal is sent from the receiving side and the next transmit data is ready to be transferred to TDR. [Setting conditions] •...
Page 492: Smart Card Mode Register (Scmr)
Section 13 Serial Communication Interface (SCI) 13.3.8 Smart Card Mode Register (SCMR) SCMR selects smart card interface mode and its format.      Bit Name SDIR SINV SMIF Initial Value Initial Bit Name Value Description  7 to 4 All 1 Reserved These are read-only bits and cannot be modified.
Page 493: Bit Rate Register (Brr)
Section 13 Serial Communication Interface (SCI) 13.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 13.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode, and smart card interface mode.
Page 494 Section 13 Serial Communication Interface (SCI) Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency Pφ (MHz) 9.8304 Bit Rate Error Error Error Error (bit/s) 0.03 –0.26 –0.25 0.03 0.16 0.00 0.16 0.16 0.16 0.00 0.16 0.16...
Page 495 Section 13 Serial Communication Interface (SCI) Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency Pφ (MHz) 17.2032 19.6608 Bit Rate Error Error Error Error (bit/s) 0.48 –0.12 0.31 –0.25 0.00 0.16 0.00 0.16 0.00 0.16 0.00...
Page 496 Section 13 Serial Communication Interface (SCI) Table 13.4 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode) Pφ (MHz) Maximum Bit Rate (bit/s) 250000 9.8304 307200 312500 375000 12.288 384000 437500 14.7456 460800 500000 17.2032 537600 562500 19.6608 614400 625000 781250 937500 1031250...
Page 497 Section 13 Serial Communication Interface (SCI) Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Pφ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 2.0000 125000 9.8304 2.4576 153600 2.5000 156250 3.0000 187500 12.288 3.0720 192000 3.5000 218750 14.7456 3.6864...
Page 498 Section 13 Serial Communication Interface (SCI) Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency Pφ (MHz) Bit Rate (bit/s)           2.5k 100k 250k 500k 2.5M Rev.2.00 Jun. 28, 2007 Page 476 of 666 REJ09B0311-0200...
Page 499 Section 13 Serial Communication Interface (SCI) Operating Frequency Pφ (MHz) Bit Rate (bit/s) 2.5k 100k 250k       500k               2.5M   ...
Page 500 Section 13 Serial Communication Interface (SCI) Table 13.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) Operating Frequency Pφ (MHz) 7.1424 10.00 10.7136 13.00 Bit Rate (bit/s) Error (%) n Error (%) n Error (%) n Error (%) 9600...
Page 501: Serial Extended Mode Register (Semr)
Section 13 Serial Communication Interface (SCI) 13.3.10 Serial Extended Mode Register (SEMR) SEMR selects the clock source in asynchronous mode. The basic clock is automatically specified when the average transfer rate operation is selected.     Bit Name ABCS ACS2 ACS1...
Page 502 Section 13 Serial Communication Interface (SCI) Initial Bit Name Value Description ACS2 Asynchronous Mode Clock Source Select (valid when CKE1 = 1 in asynchronous mode) ACS1 These bits select the clock source for the average ACS0 transfer rate function. When the average transfer rate function is enabled, the basic clock is automatically specified regardless of the ABCS bit value.
Page 503: Operation In Asynchronous Mode
Section 13 Serial Communication Interface (SCI) 13.4 Operation in Asynchronous Mode Figure 13.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level).
Page 504: Data Transfer Format
Section 13 Serial Communication Interface (SCI) 13.4.1 Data Transfer Format Table 13.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 13.5, Multiprocessor Communication Function.
Page 505: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
Section 13 Serial Communication Interface (SCI) 13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Page 506: Clock
Section 13 Serial Communication Interface (SCI) 13.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR.
Page 507: Sci Initialization (Asynchronous Mode)
Section 13 Serial Communication Interface (SCI) 13.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 13.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change.
Page 508: Serial Data Transmission (Asynchronous Mode)
Section 13 Serial Communication Interface (SCI) 13.4.5 Serial Data Transmission (Asynchronous Mode) Figure 13.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 509 Section 13 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin. After the TE bit is set to 1, a 1 is output for a frame, and transmission is enabled.
Page 510: Serial Data Reception (Asynchronous Mode)
Section 13 Serial Communication Interface (SCI) 13.4.6 Serial Data Reception (Asynchronous Mode) Figure 13.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, stores receive data in RSR, and checks the parity bit and stop bit.
Page 511 Section 13 Serial Communication Interface (SCI) Table 13.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.
Page 512 Section 13 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input Start reception pin. [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
Page 513 Section 13 Serial Communication Interface (SCI) Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 PER = 1 Parity error processing Clear ORER, PER, and FER flags in SSR to 0 <End>...
Page 514: Multiprocessor Communication Function
Section 13 Serial Communication Interface (SCI) 13.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data.
Page 515 Section 13 Serial Communication Interface (SCI) Transmitting station Communication line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle =...
Page 516: Multiprocessor Serial Data Transmission
Section 13 Serial Communication Interface (SCI) 13.5.1 Multiprocessor Serial Data Transmission Figure 13.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission.
Page 517: Multiprocessor Serial Data Reception
Section 13 Serial Communication Interface (SCI) 13.5.2 Multiprocessor Serial Data Reception Figure 13.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR.
Page 518 Section 13 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input pin. Start reception [2] ID reception cycle: Set the MPIE bit in SCR to 1. Set MPIE bit in SCR to 1 [3] SCI state check, ID reception and comparison: Read ORER and FER flags in SSR...
Page 519 Section 13 Serial Communication Interface (SCI) Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev.2.00 Jun.
Page 520: Operation In Clocked Synchronous Mode
Section 13 Serial Communication Interface (SCI) 13.6 Operation in Clocked Synchronous Mode Figure 13.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next.
Page 521: Sci Initialization (Clocked Synchronous Mode)
Section 13 Serial Communication Interface (SCI) 13.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 13.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change.
Page 522: Serial Data Transmission (Clocked Synchronous Mode)
Section 13 Serial Communication Interface (SCI) 13.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 13.16 shows an example of the operation for transmission in clocked synchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 523 Section 13 Serial Communication Interface (SCI) Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt Data written to TDR TXI interrupt TEI interrupt request request generated and TDRE flag cleared request generated generated...
Page 524: Serial Data Reception (Clocked Synchronous Mode)
Section 13 Serial Communication Interface (SCI) 13.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 13.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR.
Page 525 Section 13 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The RxD pin is automatically designated as the receive data input pin. Start reception [2] [3] Receive error processing: If a receive error occurs, read the Read ORER flag in SSR ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0.
Page 526: Simultaneous Serial Data Transmission And Reception (Clocked Synchronous Mode)
Section 13 Serial Communication Interface (SCI) 13.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 13.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations.
Page 527 Section 13 Serial Communication Interface (SCI) [1] SCI initialization: Initialization The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the Start transmission/reception receive data input pin, enabling simultaneous transmit and receive operations.
Page 528: Operation In Smart Card Interface Mode
Section 13 Serial Communication Interface (SCI) 13.7 Operation in Smart Card Interface Mode The SCI supports the IC card (smart card) interface, supporting the ISO/IEC 7816-3 (Identification Card) standard, as an extended serial communication interface function. Smart card interface mode can be selected using the appropriate register. 13.7.1 Sample Connection Figure 13.21 shows a sample connection between the smart card and this LSI.
Page 529: Data Format (Except In Block Transfer Mode)
Section 13 Serial Communication Interface (SCI) 13.7.2 Data Format (Except in Block Transfer Mode) Figure 13.22 shows the data transfer formats in smart card interface mode. • One frame contains 8-bit data and a parity bit in asynchronous mode. • During transmission, at least 2 etu (elementary time unit: time required for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame.
Page 530: Block Transfer Mode
Section 13 Serial Communication Interface (SCI) For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 13.23. Therefore, data in the start character in the figure is H'3B.
Page 531: Receive Data Sampling Timing And Reception Margin
Section 13 Serial Communication Interface (SCI) 13.7.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card interface mode. In this mode, the SCI can operate on a basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 bit settings (the frequency is always 16 times the bit rate in normal asynchronous mode).
Page 532: Initialization
Section 13 Serial Communication Interface (SCI) 13.7.5 Initialization Before transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. 1. Clear the TE and RE bits in SCR to 0. 2.
Page 533: Data Transmission (Except In Block Transfer Mode)
Section 13 Serial Communication Interface (SCI) 13.7.6 Data Transmission (Except in Block Transfer Mode) Data transmission in smart card interface mode (except in block transfer mode) is different from that in normal serial communication interface mode in that an error signal is sampled and data can be re-transmitted.
Page 534 Section 13 Serial Communication Interface (SCI) (n + 1) th nth transfer frame Retransfer frame transfer frame (DE) D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 TDRE Transfer from TDR to TSR Transfer from TDR to TSR...
Page 535 Section 13 Serial Communication Interface (SCI) Start Initialization Start transmission ERS = 0 ? Error processing TEND = 1 ? Write data to TDR and clear TDRE flag in SSR to 0 All data transmitted? ERS = 0 ? Error processing TEND = 1 ? Clear TE bit in SCR to 0 Figure 13.28 Sample Transmission Flowchart...
Page 536: Serial Data Reception (Except In Block Transfer Mode)
Section 13 Serial Communication Interface (SCI) 13.7.7 Serial Data Reception (Except in Block Transfer Mode) Data reception in smart card interface mode is similar to that in normal serial communication interface mode. Figure 13.29 shows the data re-transfer operation during reception. 1.
Page 537: Clock Output Control
Section 13 Serial Communication Interface (SCI) Start Initialization Start reception ORER = 0 and PER = 0? Error processing RDRF = 1 ? Read data from RDR and clear RDRF flag in SSR to 0 All data received? Clear RE bit in SCR to 0 Figure 13.30 Sample Reception Flowchart 13.7.8 Clock Output Control...
Page 538 Section 13 Serial Communication Interface (SCI) At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty cycle. • At power-on To secure the appropriate clock duty cycle simultaneously with power-on, use the following procedure.
Page 539: Interrupt Sources
Section 13 Serial Communication Interface (SCI) 13.8 Interrupt Sources 13.8.1 Interrupts in Normal Serial Communication Interface Mode Table 13.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR.
Page 540: Interrupts In Smart Card Interface Mode
Section 13 Serial Communication Interface (SCI) 13.8.2 Interrupts in Smart Card Interface Mode Table 13.13 shows the interrupt sources in smart card interface mode. A transmit end (TEI) interrupt request cannot be used in this mode. Table 13.13 SCI Interrupt Sources Name Interrupt Source Interrupt Flag...
Page 541: Usage Notes
Section 13 Serial Communication Interface (SCI) 13.9 Usage Notes 13.9.1 Module Stop State Setting Operation of the SCI can be disabled or enabled using the module stop control register. The initial setting is for operation of the SCI to be halted. Register access is enabled by clearing module stop state.
Page 542: Relation Between Writing To Tdr And Tdre Flag
Section 13 Serial Communication Interface (SCI) 13.9.5 Relation between Writing to TDR and TDRE Flag The TDRE flag in SSR is a status flag which indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR irrespective of the TDRE flag status.
Page 543: Sci Operations During Power-Down State
Section 13 Serial Communication Interface (SCI) 13.9.7 SCI Operations during Power-Down State Transmission Before specifying the module stop state or making a transition to software standby mode, stop the transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins in the module stop state or in software standby mode depend on the port settings, and the pins output a high-level signal after cancellation.
Page 544 Section 13 Serial Communication Interface (SCI) Transmission [1] Data being transmitted is lost All data transmitted? halfway. Data can be normally transmitted from the CPU by setting the TE bit to 1, reading SSR, writing to TDR, and Read TEND flag in SSR clearing the TDRE bit to 0 after clearing software standby mode;...
Page 545 Section 13 Serial Communication Interface (SCI) Transition to Software standby Transmission start Transmission end software standby mode canceled mode TE bit Port output pin input/output Port Marking output Port input/output High output* Last TxD bit retained input/output output pin SCI TxD output Port Port TxD output...
Page 546 Section 13 Serial Communication Interface (SCI) Rev.2.00 Jun. 28, 2007 Page 524 of 666 REJ09B0311-0200...
Page 547: Section 14 A/D Converter
Section 14 A/D Converter Section 14 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. Figure 14.1 shows a block diagram of the A/D converter. 14.1 Features •...
Page 548 Section 14 A/D Converter Internal Module data bus data bus 10-bit A/D Vref – Comparator Control circuit Sample-and- hold circuit ADI0 interrupt signal ADTRG0 Conversion start trigger from the TPU or TMR [Legend] ADDRD: A/D data register D ADCR: A/D control register ADDRE: A/D data register E ADCSR: A/D control/status register ADDRF: A/D data register F...
Page 549: Input/Output Pins
Section 14 A/D Converter 14.2 Input/Output Pins Table 14.1 shows the pin configuration of the A/D converter. Table 14.1 Pin Configuration Pin Name Symbol Function Analog input pin 0 Input Analog inputs Analog input pin 1 Input Analog input pin 2 Input Analog input pin 3 Input...
Page 550: A/D Data Registers A To H (Addra To Addrh)
Section 14 A/D Converter 14.3.1 A/D Data Registers A to H (ADDRA to ADDRH) There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 14.2.
Page 551: A/D Control/Status Register (Adcsr)
Section 14 A/D Converter 14.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations.  Bit Name ADIE ADST Initial Value R/(W)* Note: * Only 0 can be written to this bit, to clear the flag. Initial Bit Name Value Description R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion.
Page 552 Section 14 A/D Converter Initial Bit Name Value Description Channel Select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR. • When SCANE = 0 and SCANS = X 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5...
Page 553: A/D Control Register (Adcr)
Section 14 A/D Converter 14.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion to be started by an external trigger input.   Bit Name TRGS1 TRGS0 SCANE SCANS CKS1 CKS0 Initial Value Initial Bit Name Value Description TRGS1 Timer Trigger Select 1 and 0 TRGS0 These bits select enabling or disabling of the start of A/D conversion by a trigger signal.
Page 554: Operation
Section 14 A/D Converter Initial Bit Name Value Description  1, 0 All 0 Reserved These are read-only bits and cannot be modified. [Legend] Don't care To set A/D conversion to start by the ADTRG0 pin, the DDR bit and ICR bit for the Note: corresponding pin should be set to 0 and 1, respectively.
Page 555: Scan Mode
Section 14 A/D Converter ADIE A/D conversion start ADST Clear Clear Channel 0 (AN0) Waiting for conversion operation state Waiting for Channel 1 (AN1) A/D conversion 1 Waiting for conversion A/D conversion 2 Waiting for conversion conversion operation state Channel 2 (AN2) Waiting for conversion operation state Channel 3 (AN3)
Page 556 Section 14 A/D Converter 3. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. A/D conversion of the first channel in the group starts again.
Page 557: Input Sampling And A/D Conversion Time
Section 14 A/D Converter 14.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (t ) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion.
Page 558 Section 14 A/D Converter Table 14.3 A/D Conversion Characteristics (Single Mode) CKS1 = 0 CKS1 = 1 CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1 Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Ma Item Symbol ...
Page 559: External Trigger Input Timing
Section 14 A/D Converter 14.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in ADCR, an external trigger is input from the ADTRG0 pin. A/D conversion starts when the ADST bit in ADCSR is set to 1 on the falling edge of the ADTRG0 pin.
Page 560: A/D Conversion Accuracy Definitions
Section 14 A/D Converter 14.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes. • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 14.6). •...
Page 561 Section 14 A/D Converter Digital output Ideal A/D conversion characteristic Quantization error 1022 1023 1024 1024 1024 1024 Analog input voltage Figure 14.6 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error...
Page 562: Usage Notes
Section 14 A/D Converter 14.7 Usage Notes 14.7.1 Module Stop State Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing the module stop state.
Page 563: Influences On Absolute Accuracy
Section 14 A/D Converter 14.7.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, acting as antennas.
Page 564: Notes On Noise Countermeasures
Section 14 A/D Converter 14.7.6 Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) should be connected between AVcc and AVss as shown in figure 14.9.
Page 565: A/D Input Hold Function In Software Standby Mode
Section 14 A/D Converter 10 kΩ AN0 to AN7 To A/D converter 20 pF Note: Values are reference values. Figure 14.10 Analog Input Pin Equivalent Circuit 14.7.7 A/D Input Hold Function in Software Standby Mode When this LSI enters software standby mode with A/D conversion enabled, the analog inputs are retained, and the analog power supply current is equal to as during A/D conversion.
Page 566 Section 14 A/D Converter Rev.2.00 Jun. 28, 2007 Page 544 of 666 REJ09B0311-0200...
Page 567: Section 15 D/A Converter
Section 15 D/A Converter Section 15 D/A Converter 15.1 Features • 8-bit resolution • Two output channels • Maximum conversion time of 10 µs (with 20 pF load) • Output voltage of 0 V to V • D/A output hold function in software standby mode •...
Page 568: Input/Output Pins
Section 15 D/A Converter 15.2 Input/Output Pins Table 15.1 shows the pin configuration of the D/A converter. Table 15.1 Pin Configuration Pin Name Symbol Function Analog power supply pin Input Analog block power supply Analog ground pin Input Analog block ground Reference voltage pin Vref Input...
Page 569: D/A Control Register 01 (Dacr01)
Section 15 D/A Converter 15.3.2 D/A Control Register 01 (DACR01) DACR01 controls the operation of the D/A converter.      DAOE1 DAOE0 Bit Name Initial Value Initial Bit Name Value Description DAOE1 D/A Output Enable 1 Controls D/A conversion and analog output. 0: Analog output of channel 1 (DA1) is disabled 1: D/A conversion of channel 1 is enabled.
Page 570 Section 15 D/A Converter Table 15.2 Control of D/A Conversion Bit 5 Bit 7 Bit 6 DAOE1 DAOE0 Description D/A conversion is disabled. D/A conversion of channel 0 is enabled and D/A conversion of channel 1 is disabled. Analog output of channel 0 (DA0) is enabled and analog output of channel 1 (DA1) is disabled.
Page 571: Operation
Section 15 D/A Converter 15.4 Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. When the DAOE bit in DACR01 is set to 1, D/A conversion is enabled and the conversion result is output. An operation example of D/A conversion on channel 0 is shown below.
Page 572: Usage Notes
Section 15 D/A Converter 15.5 Usage Notes 15.5.1 Module Stop State Setting Operation of the D/A converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the D/A converter to be halted. Register access is enabled by clearing the module stop state.
Page 573: Section 16 Ram
Section 16 RAM Section 16 RAM This LSI has a 24-kbyte on-chip high-speed static RAM. The RAM is connected to the CPU by a 32-bit data bus, enabling one-state access by the CPU to all byte data, word data, and longword data.
Page 574 Section 16 RAM Rev.2.00 Jun. 28, 2007 Page 552 of 666 REJ09B0311-0200...
Page 575: Section 17 Clock Pulse Generator
Section 17 Clock Pulse Generator Section 17 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (Iφ), peripheral module clock (Pφ), and external bus clock (Bφ). The clock pulse generator consists of an oscillator, PLL (Phase Locked Loop) circuit, divider, and selector circuit.
Page 576: Register Description
Section 17 Clock Pulse Generator 17.1 Register Description The clock pulse generator has the following register. • System clock control register (SCKCR) 17.1.1 System Clock Control Register (SCKCR) SCKCR controls Bφ clock output and frequencies of the system, peripheral module, and external bus clocks.
Page 577 Section 17 Clock Pulse Generator Initial Bit Name Value Description ICK2 System Clock (Iφ) Select ICK1 These bits select the frequency of the system clock provided to the CPU and DTC. The ratio to the input clock ICK0 is as follows: 000: ×...
Page 578 Section 17 Clock Pulse Generator Initial Bit Name Value Description BCK2 External Bus Clock (Bφ) Select BCK1 These bits select the frequency of the external bus clock. The ratio to the input clock is as follows: BCK0 000: × 4 001: ×...
Page 579: Oscillator
Section 17 Clock Pulse Generator 17.2 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 17.2.1 Connecting Crystal Resonator A crystal resonator can be connected as shown in the example in figure 17.2. Select the damping resistance R according to table 17.1.
Page 580: External Clock Input
Section 17 Clock Pulse Generator Table 17.2 Crystal Resonator Characteristics Frequency (MHz) Max. (Ω) Max. (pF) 17.2.2 External Clock Input An external clock signal can be input as shown in the examples in figure 17.4. If the XTAL pin is left open, make sure that parasitic capacitance is no more than 10 pF.
Page 581: Usage Notes
Section 17 Clock Pulse Generator 17.5 Usage Notes 17.5.1 Notes on Clock Pulse Generator 1. The following points should be noted since the frequency of φ (Iφ: system clock, Pφ: peripheral module clock, Bφ: external bus clock) supplied to each module changes according to the setting of SCKCR.
Page 582: Notes On Resonator
Section 17 Clock Pulse Generator One cycle (worst case) after the bus cycle completion External clock Iφ Bus master Operating clock Operating clock changed specified in SCKCR Figure 17.5 Clock Modification Timing 17.5.2 Notes on Resonator Since various characteristics related to the resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a reference.
Page 583 Section 17 Clock Pulse Generator Figure 17.7 shows the external circuitry recommended for the PLL circuit. Separate PLLVcc and PLLVss from the other Vcc and Vss lines at the board power supply source, and be sure to insert bypass capacitors CPB and CB close to the pins. Rp: 100 Ω...
Page 584 Section 17 Clock Pulse Generator Rev.2.00 Jun. 28, 2007 Page 562 of 666 REJ09B0311-0200...
Page 585: Section 18 Power-Down States
Section 18 Power-Down States Section 18 Power-Down States This LSI has power consumption reduction functions, such as multi-clock function, module stop function, and transition function to the power-down state. 18.1 Features • Multi-clock function The frequency division ratio is settable independently for the system clock, peripheral module clock, and external bus clock.
Page 586 Section 18 Power-Down States Table 18.1 Operating States All-Module-Clock- Software Standby Hardware Operating State Sleep Mode Stop Mode Mode Standby Mode Transition Control register + Control register + Control register + Pin input condition instruction instruction instruction Cancellation Interrupt Interrupt* External interrupt method Oscillator...
Page 587: Register Descriptions
Section 18 Power-Down States STBY pin = low STBY pin = high Reset state Hardware standby mode RES pin = low SSBY = 0 RES pin = high SLEEP Sleep mode instruction* SSBY = 0, ACSE = 1 All interrupts MSTPCR = H'F[0-F]FFFFFF SLEEP instruction* All-module-clock-...
Page 588: Standby Control Register (Sbycr)
Section 18 Power-Down States 18.2.1 Standby Control Register (SBYCR) SBYCR controls software standby mode.  Bit Name SSBY STS4 STS3 STS2 STS1 STS0 Initial Value        Bit Name SLPIE Initial Value Initial Bit Name Value Description SSBY...
Page 589 Section 18 Power-Down States Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. STS4 Standby Timer Select 4 to 0 STS3 These bits select the time the MCU waits for the clock to settle when software standby mode is cleared by an STS2 external interrupt.
Page 590 Section 18 Power-Down States Initial Bit Name Value Description SLPIE Sleep Instruction Exception Handling Enable Selects whether the execution of a SLEEP instruction causes sleep instruction exception handling or causes a transition to the power-down state. 0: The execution of a SLEEP instruction causes a transition to the power-down state.
Page 591: Module Stop Control Registers A And B (Mstpcra And Mstpcrb)
Section 18 Power-Down States 18.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) MSTPCRA and MSTPCRB control module stop function. Setting a bit to 1 makes the corresponding module enter the module stop state, while clearing the bit to 0 clears the module stop state.
Page 592 Section 18 Power-Down States • MSTPCRA Initial Bit Name Value Module ACSE All-Module-Clock-Stop Mode Enable Enables/disables all-module-clock-stop mode to reduce current consumption by stopping the bus controller and I/O ports operations when the CPU executes the SLEEP instruction after the module stop state has been set for all the on-chip peripheral modules controlled by MSTPCR.
Page 593 Section 18 Power-Down States • MSTPCRB Initial Bit Name Value Module MSTPB15 1 Programmable pulse generator (PPG) MSTPB14 Reserved MSTPB13 These bits are always read as 1. The write value should always be 1. MSTPB12 1 Serial communication interface_4 (SCI_4) MSTPB11 1 Reserved This bit is always read as 1.
Page 594: Module Stop Control Register C (Mstpcrc)
Section 18 Power-Down States 18.2.3 Module Stop Control Register C (MSTPCRC) When bits MSTPC2 to MSTPC0 are set to 1, the corresponding on-chip RAM stops. Do not set the corresponding MSTPC2 to MSTPC0 bits to 1 while accessing on-chip RAM. Bit Name MSTPC15 MSTPC14...
Page 595: Multi-Clock Function
Section 18 Power-Down States 18.3 Multi-Clock Function When bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to BCK0 in SCKCR are set, the clock frequency changes at the end of the bus cycle. The CPU and bus masters operate on the operating clock specified by bits ICK2 to ICK0.
Page 596: Sleep Mode
Section 18 Power-Down States 18.5 Sleep Mode 18.5.1 Transition to Sleep Mode When the SLEEP instruction is executed when the SSBY bit in SBYCR is 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained.
Page 597: All-Module-Clock-Stop Mode
Section 18 Power-Down States 18.6 All-Module-Clock-Stop Mode When the ACSE bit is set to 1 and all modules controlled by MSTPCR are stopped (MSTPCRA, MSTPCRB = H'FFFFFFFF), or all modules except for the 8-bit timer are stopped (MSTPCRA, MSTPCRB = H'F[0 to F]FFFFFF), executing a SLEEP instruction with the SSBY bit in SBYCR cleared to 0 will cause all modules (except for the 8-bit timer* and watchdog timer), the bus controller, and the I/O ports to stop operating, and to make a transition to all-module-clock-stop mode at the end of the bus cycle.
Page 598: Clearing Software Standby Mode
Section 18 Power-Down States 18.7.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ11*), or by means of the RES pin or STBY pin. 1. Clearing by interrupt When an NMI or IRQ0 to IRQ11* interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS4 to STS0 in SBYCR, stable clocks are supplied to the entire LSI, software standby mode is cleared, and interrupt exception handling is started.
Page 599 Section 18 Power-Down States Table 18.2 Oscillation Settling Time Settings Pφ* [MHz] Standby STS4 STS3 STS2 STS1 STS0 Time Unit Reserved    µs Reserved    Reserved    Reserved    Reserved   ...
Page 600 Section 18 Power-Down States Pφ* [MHz] Standby STS4 STS3 STS2 STS1 STS0 Time Unit Reserved    µs Reserved    Reserved    Reserved    Reserved    39.4 51.2 64.0 1024 78.8 102.4 128.0 2048...
Page 601: Software Standby Mode Application Example
Section 18 Power-Down States 18.7.4 Software Standby Mode Application Example Figure 18.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin.
Page 602: Hardware Standby Mode
Section 18 Power-Down States 18.8 Hardware Standby Mode 18.8.1 Transition to Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power consumption.
Page 603: Timing Sequence At Power-On
Section 18 Power-Down States 18.8.4 Timing Sequence at Power-On Figure 18.4 shows the timing sequence at power-on. At power-on, the RES pin must be driven low with the STBY pin driven high for a given time in order to clear the reset state. To enter hardware standby mode immediately after power-on, drive the STBY pin low after exiting the reset state.
Page 604: Sleep Instruction Exception Handling
Section 18 Power-Down States 18.9 Sleep Instruction Exception Handling Sleep instruction exception handling is exception handling initiated by the execution of a SLEEP instruction. Sleep instruction exception handling is always accepted while the program is in execution. When the SLPIE bit is set to 0, the execution of a SLEEP instruction does not initiate sleep instruction exception handling.
Page 605 Section 18 Power-Down States SLPIE = 0 Instruction before SLEEP instruction SLEEP instruction executed (SLPIE = 0) Power-down state Transition by exception handling Canceling factor interrupt Interrupt handling RTE instruction executed Instruction after SLEEP instruction Figure 18.5 When Canceling Factor Interrupt is Generated after SLEEP Instruction Execution SLPIE = 0 Instruction before SLEEP instruction...
Page 606 Section 18 Power-Down States SLPIE = 0 Instruction before SLEEP instruction Transition by exception handling Canceling factor interrupt SLPIE = 1 Interrupt handling SSBY = 0 RTE instruction executed SLEEP instruction executed (SLPIE = 1) Transition by exception handling Sleep instruction exceotion handling Vector Number 18 Exception servise routine...
Page 607: Bφ Clock Output Control
Section 18 Power-Down States 18.10 Bφ Clock Output Control Output of the Bφ clock can be controlled by bits PSTOP1 and POSEL1 in SCKCR, and DDR for the corresponding PA7 pin. Clearing both bits PSTOP1 and POSEL1 to 0 enables the Bφ clock output on the PA7 pin. When bit PSTOP1 is set to 1, the Bφ...
Page 608: Usage Notes
Section 18 Power-Down States 18.11 Usage Notes 18.11.1 I/O Port Status In software standby mode, the I/O port states are retained. Therefore, there is no reduction in current consumption for the output current when a high-level signal is output. 18.11.2 Current Consumption during Oscillation Settling Standby Period Current consumption increases during the oscillation settling standby period.
Page 609: Section 19 List Of Registers
Section 19 List of Registers Section 19 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below.
Page 610: Register Addresses (Address Order)
Section 19 List of Registers 19.1 Register Addresses (Address Order) Access Number Data Cycles Register Name Abbreviation of Bits Address Module Width (Read/Write) Port 1 data direction register P1DDR H'FFB80 I/O port 2Pφ/2Pφ Port 2 data direction register P2DDR H'FFB81 I/O port 2Pφ/2Pφ...
Page 611 Section 19 List of Registers Access Number Data Cycles Register Name Abbreviation of Bits Address Module Width (Read/Write) Port D pull-up MOS control register PDPCR H'FFBB4 I/O port 2Pφ/2Pφ Port E pull-up MOS control register PEPCR H'FFBB5 I/O port 2Pφ/2Pφ Port F pull-up MOS control register PFPCR H'FFBB6 I/O port...
Page 612 Section 19 List of Registers Access Number Data Cycles Register Name Abbreviation of Bits Address Module Width (Read/Write) DTC vector base register DTCVBR H'FFD80 2Iφ/3Iφ Bus width control register ABWCR H'FFD84 2Iφ/3Iφ Access state control register ASTCR H'FFD86 2Iφ/3Iφ Wait control register A WTCRA H'FFD88 2Iφ/3Iφ...
Page 613 Section 19 List of Registers Access Number Data Cycles Register Name Abbreviation of Bits Address Module Width (Read/Write) Timer control register_2 TCR_2 H'FFEC0 TMR_2 2Pφ/2Pφ Timer control register_3 TCR_3 H'FFEC1 TMR_3 2Pφ/2Pφ Timer control/status register_2 TCSR_2 H'FFEC2 TMR_2 2Pφ/2Pφ Timer control/status register_3 TCSR_3 H'FFEC3 TMR_3...
Page 614 Section 19 List of Registers Access Number Data Cycles Register Name Abbreviation of Bits Address Module Width (Read/Write) DTC enable register A DTCERA H'FFF20 INTC 2Iφ/3Iφ DTC enable register B DTCERB H'FFF22 INTC 2Iφ/3Iφ DTC enable register C DTCERC H'FFF24 INTC 2Iφ/3Iφ...
Page 615 Section 19 List of Registers Access Number Data Cycles Register Name Abbreviation of Bits Address Module Width (Read/Write) Port A data register PADR H'FFF59 I/O port 2Pφ/2Pφ Port B data register PBDR H'FFF5A I/O port 2Pφ/2Pφ Port D data register PDDR H'FFF5C I/O port...
Page 616 Section 19 List of Registers Access Number Data Cycles Register Name Abbreviation of Bits Address Module Width (Read/Write) Serial mode register_0 SMR_0 H'FFF80 SCI_0 2Pφ/2Pφ Bit rate register_0 BRR_0 H'FFF81 SCI_0 2Pφ/2Pφ Serial control register_0 SCR_0 H'FFF82 SCI_0 2Pφ/2Pφ Transmit data register_0 TDR_0 H'FFF83 SCI_0...
Page 617 Section 19 List of Registers Access Number Data Cycles Register Name Abbreviation of Bits Address Module Width (Read/Write) Timer control/status register_1 TCSR_1 H'FFFB3 TMR_1 2Pφ/2Pφ Time constant register A_0 TCORA_0 H'FFFB4 TMR_0 2Pφ/2Pφ Time constant register A_1 TCORA_1 H'FFFB5 TMR_1 2Pφ/2Pφ...
Page 618 Section 19 List of Registers Access Number Data Cycles Register Name Abbreviation of Bits Address Module Width (Read/Write) Timer control register_2 TCR_2 H'FFFE0 TPU_2 2Pφ/2Pφ Timer mode register_2 TMDR_2 H'FFFE1 TPU_2 2Pφ/2Pφ Timer I/O control register_2 TIOR_2 H'FFFE2 TPU_2 2Pφ/2Pφ Timer interrupt enable register_2 TIER_2 H'FFFE4...
Page 619: Register Bits
Section 19 List of Registers 19.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. Register Abbreviation 31/23/15/7 30/22/14/6...
Page 620 Section 19 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module PDPCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR I/O port PEPCR PE7PCR PE6PCR PE6PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR PFPCR PF7PCR PF6PCR PF5PCR PF4PCR PF3PCR PF2PCR...
Page 621 Section 19 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module         ISCRH IRQ11SR IRQ11SF IRQ10SR IRQ10SF IRQ9SR IRQ9SF IRQ8SR IRQ8SF ISCRL IRQ7SR IRQ7SF IRQ6SR IRQ6SF IRQ5SR IRQ5SF IRQ4SR IRQ4SF IRQ3SR...
Page 622 Section 19 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module      MDCR MDS2 MDS1 MDS0 SYSTEM            FETCHMD  SYSCR MACS EXPE RAME...
Page 623 Section 19 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module  TCR_4 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_4      TMDR_4 TIOR_4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 ...
Page 624 Section 19 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module DTCERH DTCE15 DTCE14 DTCE13 DTCE12 DTCE11 DTCE10 DTCE9 DTCE8 INTC DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0      DTCCR RCHNE ...
Page 625 Section 19 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module DADR0 DADR1      DACR01 DAOE1 DAOE0 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV NDERH...
Page 626 Section 19 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module ADDRD ADDRE ADDRF ADDRG ADDRH  ADCSR ADIE ADST   ADCR TRGS1 TRGS0 SCANE SCANS CKS1 CKS0   TCSR WT/IT CKS2 CKS1 CKS0 TCNT ...
Page 627 Section 19 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module TCNT_0 TPU_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0  TCR_1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_1      TMDR_1 TIOR_1 IOB3 IOB2 IOB1 IOB0...
Page 628 Section 19 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module TCR_3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_3    TMDR_3 TIORH_3 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_3 IOD3 IOD2 IOD1...
Page 629: Register States In Each Operating Mode
Section 19 List of Registers 19.3 Register States in Each Operating Mode All-Module- Software Hardware Register Module Sleep Clock-Stop Standby Standby Abbreviation Reset Stop State Mode Mode Mode Mode Module     P1DDR Initialized Initialized I/O port  ...
Page 630 Section 19 List of Registers All-Module- Software Hardware Register Module Sleep Clock-Stop Standby Standby Abbreviation Reset Stop State Mode Mode Mode Mode Module     PDPCR Initialized Initialized I/O port     PEPCR Initialized Initialized  ...
Page 631 Section 19 List of Registers All-Module- Software Hardware Register Module Sleep Clock-Stop Standby Standby Abbreviation Reset Stop State Mode Mode Mode Mode Module     DTCVBR Initialized Initialized     ABWCR Initialized Initialized    ...
Page 632 Section 19 List of Registers All-Module- Software Hardware Register Module Sleep Clock-Stop Standby Standby Abbreviation Reset Stop State Mode Mode Mode Mode Module     TCR_2 Initialized Initialized TMR_2     TCR_3 Initialized Initialized TMR_3  ...
Page 633 Section 19 List of Registers All-Module- Software Hardware Register Module Sleep Clock-Stop Standby Standby Abbreviation Reset Stop State Mode Mode Mode Mode Module     DTCERA Initialized Initialized INTC     DTCERB Initialized Initialized   ...
Page 634 Section 19 List of Registers All-Module- Software Hardware Register Module Sleep Clock-Stop Standby Standby Abbreviation Reset Stop State Mode Mode Mode Mode Module     PADR Initialized Initialized I/O port     PBDR Initialized Initialized  ...
Page 635 Section 19 List of Registers All-Module- Software Hardware Register Module Sleep Clock-Stop Standby Standby Abbreviation Reset Stop State Mode Mode Mode Mode Module     SMR_1 Initialized Initialized SCI_1     BRR_1 Initialized Initialized   ...
Page 636 Section 19 List of Registers All-Module- Software Hardware Register Module Sleep Clock-Stop Standby Standby Abbreviation Reset Stop State Mode Mode Mode Mode Module     TCNT_0 Initialized Initialized TMR_0     TCNT_1 Initialized Initialized TMR_1  ...
Page 637 Section 19 List of Registers All-Module- Software Hardware Register Module Sleep Clock-Stop Standby Standby Abbreviation Reset Stop State Mode Mode Mode Mode Module     TSR_2 Initialized Initialized TPU_2     TCNT_2 Initialized Initialized   ...
Page 638 Section 19 List of Registers Rev.2.00 Jun. 28, 2007 Page 616 of 666 REJ09B0311-0200...
Page 639: Section 20 Electrical Characteristics
Section 20 Electrical Characteristics Section 20 Electrical Characteristics 20.1 Absolute Maximum Ratings Table 20.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +4.6 Input voltage (except port 5) –0.3 to V +0.3 Input voltage (port 5) –0.3 to AV +0.3 Reference power supply voltage...
Page 640: Dc Characteristics
Section 20 Electrical Characteristics 20.2 DC Characteristics Table 20.2 DC Characteristics (1) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Test Item...
Page 641 Section 20 Electrical Characteristics Table 20.2 DC Characteristics (2) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Test Item...
Page 642 Section 20 Electrical Characteristics Test Item Symbol Min. Typ. Max. Unit Conditions   RAM standby voltage   Vcc start voltage* CCSTART   Vcc rising gradient* ms/V Notes: 1. When the A/D and D/A converters are not used, the AV , and AV pins should not be open.
Page 643: Ac Characteristics
Section 20 Electrical Characteristics 20.3 AC Characteristics C = 30 pF RL = 2.4 kΩ LSI output pin RH = 12 kΩ Input/output timing measurement level: 1.5 V (V cc = 3.0 V to 3.6 V) Figure 20.1 Output Load Circuit Rev.2.00 Jun.
Page 644: Clock Timing
Section 20 Electrical Characteristics 20.3.1 Clock Timing Table 20.4 Clock Timing Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, Iφ = 8 MHz to 50 MHz, Bφ = 8 MHz to 50 MHz, Pφ...
Page 645 Section 20 Electrical Characteristics Oscillator Iφ NMIEG SSBY NMI exception handling Software standby mode NMI exception (power-down mode) handling Oscillation NMIEG = 1 settling time SSBY = 1 OSC2 SLEEP instruction Figure 20.3 Oscillation Settling Timing after Software Standby Mode EXTAL DEXT DEXT...
Page 646: Control Signal Timing
Section 20 Electrical Characteristics EXTAL × Figure 20.5 External Input Clock Timing 20.3.2 Control Signal Timing Table 20.5 Control Signal Timing Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, Iφ...
Page 647: Bus Timing
Section 20 Electrical Characteristics Iφ NMIS NMIH NMIW IRQi* IRQW (i = 0 to 11) IRQS IRQH IRQ* (edge input) IRQS IRQ* (level input) Note: * SSIER must be set to cancel software standby mode. Figure 20.7 Interrupt Input Timing 20.3.3 Bus Timing Table 20.6 Bus Timing (1)
Page 648 Section 20 Electrical Characteristics Test Item Symbol Min. Max. Unit Conditions RD delay time 1  Figures 20.8 to RSD1 20.20 RD delay time 2  RSD2  Read data setup time 1 RDS1  Read data setup time 2 RDS2 ...
Page 649 Section 20 Electrical Characteristics Table 20.6 Bus Timing (2) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, Bφ = 8 MHz to 50 MHz, = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Test...
Page 650 Section 20 Electrical Characteristics Bφ A23 to A0 CSD1 CS7 to CS0 RD/WR RSD1 RSD1 Read (RDNn = 1) RDS1 RDH1 D15 to D0 RD/WR RSD1 RSD2 Read (RDNn = 0) RDS2 RDH2 D15 to D0 RD/WR WRD2 WRD2 LHWR, LLWR Write WDH1 WSW1...
Page 651 Section 20 Electrical Characteristics Bφ A23 to A0 CSD1 CS7 to CS0 RD/WR RSD1 RSD1 Read (RDNn = 1) RDS1 RDH1 D15 to D0 RD/WR RSD1 RSD2 Read (RDNn = 0) RDS2 RDH2 D15 to D0 RD/WR WRD2 WRD1 LHWR, LLWR Write WDS1 WDH1...
Page 652 Section 20 Electrical Characteristics Bφ A23 to A0 CS7 to CS0 RD/WR Read (RDNn = 1) D15 to D0 RD/WR Read (RDNn = 0) D15 to D0 RD/WR LHWR, LLWR Write D15 to D0 WAIT Figure 20.10 Basic Bus Timing: Three-State Access, One Wait Rev.2.00 Jun.
Page 653 Section 20 Electrical Characteristics Bφ A23 to A0 CSD1 CS7 to CS0 RD/WR RSD1 RSD1 Read (RDNn = 1) RDS1 RDH1 D15 to D0 RD/WR RSD1 RSD2 Read (RDNn = 0) RDS2 RDH2 D15 to D0 RD/WR WRD2 WRD2 Write LHWR, LLWR WDS2 WSW1...
Page 654 Section 20 Electrical Characteristics Bφ A23 to A0 CSD1 CS7 to CS0 RD/WR RSD1 RSD1 Read (RDNn = 1) RDS1 RDH1 D15 to D0 RD/WR RSD1 RSD2 Read (RDNn = 0) RDS2 RDH2 D15 to D0 RD/WR WRD2 WRD1 LHWR, LLWR Write WDS3 WSW2...
Page 655 Section 20 Electrical Characteristics Bφ A23 to A0 CSD1 CS7 to CS0 RD/WR RSD1 RSD1 Read RDS1 RDH1 D15 to D0 LUB, LLB UBW1 RD/WR High Write WDH1 D15 to D0 Figure 20.13 Byte Control SRAM: 2-State Read/Write Access Rev.2.00 Jun. 28, 2007 Page 633 of 666 REJ09B0311-0200...
Page 656 Section 20 Electrical Characteristics Bφ A23 to A0 CSD1 CS7 to CS0 RD/WR RSD1 RSD1 Read RDS1 RDH1 D15 to D0 LUB, LLB UBW2 RD/WR High Write WDH1 D15 to D0 Figure 20.14 Byte Control SRAM: 3-State Read/Write Access Rev.2.00 Jun. 28, 2007 Page 634 of 666 REJ09B0311-0200...
Page 657 Section 20 Electrical Characteristics Bφ A23 to A6, A0 A5 to A1 CS7 to CS0 RD/WR RSD2 Read RDS2 RDH2 D15 to D0 LHWR, LLWR High Figure 20.15 Burst ROM Access Timing: 1-State Burst Access Rev.2.00 Jun. 28, 2007 Page 635 of 666 REJ09B0311-0200...
Page 658 Section 20 Electrical Characteristics Bφ A23 to A6, A0 A5 to A1 CS7 to CS0 RD/WR RSD2 Read RDS2 RDH2 D15 to D0 LHWR, LLWR High Figure 20.16 Burst ROM Access Timing: 2-State Burst Access Rev.2.00 Jun. 28, 2007 Page 636 of 666 REJ09B0311-0200...
Page 659 Section 20 Electrical Characteristics Bφ A23 to A0 CS7 to CS0 AH (AS) AHW1 RD/WR Read MAS1 RDS2 RDH2 MAD1 D15 to D0 RD/WR WSW1 LHWR, LLWR Write MAS1 WDH1 MAD1 D15 to D0 Figure 20.17 Address/Data Multiplexed Access Timing (No Wait) (Basic, 4-State Access) Rev.2.00 Jun.
Page 660 Section 20 Electrical Characteristics Bφ A23 to A0 CS7 to CS0 AH (AS) AHW2 RD/WR Read MAS2 MAD1 RDS2 RDH2 D15 to D0 RD/WR LHWR, LLWR Write MAS2 WDH1 MAD1 WDS1 D15 to D0 WAIT Figure 20.18 Address/Data Multiplexed Access Timing (Wait Control) (Address Cycle Program Wait ×...
Page 661 Section 20 Electrical Characteristics Bφ BREQS BREQS BREQ BACD BACD BACK A23 to A0 CS7 to CS0 D15 to D0 AS, RD, LHWR, LLWR Figure 20.19 External Bus Release Timing Bφ BACK BRQOD BRQOD BREQO Figure 20.20 External Bus Request Output Timing Rev.2.00 Jun.
Page 662: Timing Of On-Chip Peripheral Modules
Section 20 Electrical Characteristics 20.3.4 Timing of On-Chip Peripheral Modules Table 20.7 Timing of On-Chip Peripheral Modules Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, Pφ...
Page 663 Section 20 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions  Transmit data delay time Figure 20.30  Receive data setup time (clocked synchronous)  Receive data hold time (clocked synchronous)  Trigger input setup time Figure 20.31 TRGS converter Pφ...
Page 664 Section 20 Electrical Characteristics Pφ PO15 to PO0 Figure 20.24 PPG Output Timing Pφ TMOD TMO0 to TMO3 Figure 20.25 8-Bit Timer Output Timing Pφ TMRS TMRI0 to TMRI3 Figure 20.26 8-Bit Timer Reset Input Timing Pφ TMCS TMCS TMCI0 to TMCI3 TMCWL TMCWH Figure 20.27 8-Bit Timer Clock Input Timing...
Page 665 Section 20 Electrical Characteristics SCKW SCKr SCKf SCK0 to SCK2, SCK4 Scyc Figure 20.29 SCK Clock Input Timing SCK0 to SCK2, SCK4 TxD0 to TxD2, TxD4 (transmit data) RxD0 to RxD2, RxD4 (receive data) Figure 20.30 SCI Input/Output Timing: Clocked Synchronous Mode Pφ...
Page 666: A/D Conversion Characteristics
Section 20 Electrical Characteristics 20.4 A/D Conversion Characteristics Table 20.8 A/D Conversion Characteristics Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, Pφ = 8 MHz to 35 MHz, = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item...
Page 667: D/A Conversion Characteristics
Section 20 Electrical Characteristics 20.5 D/A Conversion Characteristics Table 20.9 D/A Conversion Characteristics Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, Pφ = 8 MHz to 35 MHz, = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item...
Page 668 Section 20 Electrical Characteristics Rev.2.00 Jun. 28, 2007 Page 646 of 666 REJ09B0311-0200...
Page 669: Appendix
Appendix Appendix Port States in Each Pin State Table A.1 Port States in Each Pin State Hardware Software Standby Mode MCU Operating Standby Bus Released Port Name Reset Mode OPE = 1 OPE = 0 Mode State Port 1 Hi-Z Hi-Z Keep Keep...
Page 670 Appendix Hardware Software Standby Mode MCU Operating Standby Bus Released Port Name Mode Reset Mode OPE = 1 OPE = 0 State PA2/ Hi-Z Hi-Z [BREQ input] [BREQ input] [BREQ input] BREQ/ Hi-Z Hi-Z Hi-Z (BREQ) WAIT [WAIT input] [WAIT input] [WAIT input] Hi-Z Hi-Z...
Page 671 Appendix Hardware Software Standby Mode MCU Operating Standby Port Name Mode Reset Mode OPE = 1 OPE = 0 Released State PB2/ Hi-Z Hi-Z [CS output] [CS output] [CS output] CS2-A/ Hi-Z Hi-Z CS6-A [Other than above] [Other than above] [Other than above] Keep Keep...
Page 672: Product Lineup
Appendix Product Lineup Product Classification Product Model Marking Package (Package Code) H8SX/1650C ROMless R5S61650CFPV R5S61650CFPV PLQP0120LA-A (FP-120BV) Rev.2.00 Jun. 28, 2007 Page 650 of 666 REJ09B0311-0200...
Page 673: Package Dimensions
Appendix Package Dimensions For the package dimensions, data in the Renesas IC Package General Catalog has priority. Figure C.1 Package Dimensions (FP-120BV) Rev.2.00 Jun. 28, 2007 Page 651 of 666 REJ09B0311-0200...
Page 674: Treatment Of Unused Pins
Appendix Treatment of Unused Pins The treatments of unused pins are listed in table D.1. Table D.1 Treatment of Unused Pins Pin Name Mode 4 Mode 5 (Always used as a reset pin) STBY • Connect to V via a pull-up resistor •...
Page 675 Appendix Pin Name Mode 4 Mode 5 • Port D Since this is the address output in its initial state, leave the pin unconnected. Port E PF4 to PF0 Port H (Used as a data bus) Port I (Used as a data bus) Since this is a general-purpose input port in its initial state, connect each pin to V...
Page 676 Appendix Rev.2.00 Jun. 28, 2007 Page 654 of 666 REJ09B0311-0200...
Page 677: Main Revisions And Additions In This Edition
Main Revisions and Additions in this Edition Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details)  Modified Type classification changed (from H8SX/1650A to H8SX/1650C). Type name and mark name changed (from R5S61650AFPV to R5S61650CFPV). 1.1 Features Modified Notes: The following additions and changes have been...
Page 678 P*/C P/C* P/C* Figure 3.1 Address Map Deleted (Advanced Mode) Notes: In the H8SX/1650, space from H'FFC000 to H'FF6000 was specified as the external address space. In the H8SX/1650C, space from H'FF0000 to H'FF6000 is specified as the access-prohibited space.
Page 679 Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) 8.2.7 Port B Modified (4) PB0/CS0/CS4-A/CS5-B Setting I/O Port Module CS0_OE CS4-A_OE Name Pin Function CS0 output  controller (initial setting) CS4-A output  8.2.10 Port F Added (1) PF7/A23/CS4-C/CS5-C/ Setting...
Page 680 Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) 8.2.10 Port F Added (3) PF5/A21/CS5-D Setting I/O Port Module CS5D_OE Name Pin Function A21_OE PF5DDR   A21 output controller CS5-D output  I/O port PF5 output PF5 input (initial setting)
Page 681 Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) 8.3.2 Port Function Control 293, Modified Register 1 (PFCR1) CS5SB CS4SA CS4SB Bit Name Description CS7 Output Pin Select CS7SA* CS7SB* 10: Specifies pin PF7 as CS7-C output 11: Setting prohibited CS6 Output Pin Select CS6SA*...
Page 682 Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) Table A.1 Port States in Each Pin 648, Modified State Software Standby Mode Hardware Released Operating Standby Port Name State Mode Reset Mode OPE = 1 OPE = 0 PB0/ External...
Page 683: Index
Index Numerics Basic bus interface ......157, 167 Big endian ..........156 0-output/1-output ........349 Bit rate............. 471 16-bit access space........165 Block diagram..........8 16-bit counter mode........ 430 Block transfer mode ........ 239 16-bit timer pulse unit (TPU) ....305 Burst ROM interface.......
Page 684 Data transfer instructions......39 Direct convention ........507 I/O ports ..........251 Double-buffered structure....... 481 ID code............ 492 DTC vector address ........ 229 Idle cycle..........198 DTC vector address offset ...... 229 Illegal instruction ........81 Index register ..........25 Initial register values.........
Page 685 Module stop mode ........583 Pull-up MOS control register....261 Multi-clock mode ........573 Multiprocessor bit........492 Multiprocessor communication function........... 492 Quantization error ........538 NMI interrupt.......... 100 RAM ............551 Nonlinearity error ........538 Read strobe (RD) timing ......176 Non-overlapping........
Page 686 IDLCR ......135, 590, 599, 609 SBYCR ....... 566, 590, 600, 609 IER.........92, 592, 602, 611 SCKCR ....... 554, 590, 600, 609 INTCR ......88, 592, 602, 611 SCMR ......470, 594, 603, 612 IPR.........90, 589, 598, 608 SCR......458, 594, 603, 612 ISCRH ......94, 589, 599, 608 SEMR ......
Page 687 Sleep mode ........564, 574 Transfer information writeback Smart card interface........ 506 skip function ........... 236 Software standby mode....564, 575 Transmit/receive data......481 Space state ..........481 Trap instruction exception handling..79 Stack status after exception handling..82 Start bit ........... 481 State transitions.........
Page 688 Rev.2.00 Jun. 28, 2007 Page 666 of 666 REJ09B0311-0200...
Page 689 Publication Date: Rev.1.00, Mar. 28, 2006 Rev.2.00, Jun. 28, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.  2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 690 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Page 692 H8SX/1650 Group Hardware Manual...

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R5s61650c H8sx/1650c

Renesas H8SX/1650 Hardware Manual

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller (BSC)

Section 7 Data Transfer Controller (DTC)

Section 8 I/O Ports

Section 9 16-Bit Timer Pulse Unit (TPU)

Section 10 Programmable Pulse Generator (PPG)

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