Section 23 Clock Pulse Generator; Figure 23.1 Block Diagram Of Clock Pulse Generator - Renesas H8S Series Hardware Manual

This LSI incorporates a clock pulse generator which generates the system clock (φ), internal clock,
bus master clock, and subclock (φSUB). The clock pulse generator consists of an oscillator, duty
correction circuit, system clock select circuit, medium-speed clock divider, bus master clock select
circuit, subclock input circuit, and subclock waveform forming circuit. Figure 23.1 shows a block
diagram of the clock pulse generator.
EXTAL
Oscillator
XTAL
Subclock
EXCL
input circuit
(ExEXCL)

Figure 23.1 Block Diagram of Clock Pulse Generator

In high-speed mode or medium-speed mode, the bus master clock is selected by software
according to the settings of the SCK2 to SCK0 bits in the standby control register (SBYCR). For
details on SBYCR, see section 24.1.1, Standby Control Register (SBYCR).
The subclock input is controlled by software according to the EXCLE bit and the EXCLS bit in
the port control register (PTCNT0) settings in the low power control register (LPWRCR). For
details on LPWRCR, see section 24.1.2, Low-Power Control Register (LPWRCR). For details on
PTCNT0, see section 8.17.1, Port Control Register 0 (PTCNT0).
CPG0500A_000020020300

Section 23 Clock Pulse Generator

φ
Duty
correction
circuit
φSUB
Subclock
waveform
forming circuit
WDT_1
count clock
Medium-
speed clock
divider
System
clock
select
φ
circuit
System clock
Internal clock
to φ pin
to on-chip
peripheral modules
Rev. 3.00 Jul. 14, 2005 Page 849 of 986
Section 23 Clock Pulse Generator
φ/2
Bus master
to φ/32
clock select
circuit
Bus master clock
to CPU, DTC, and LPC
REJ09B0098-0300