Register Descriptions; A/D Data Registers A To D (Addra To Addrd); Table 19.2 Analog Input Channels And Corresponding Addr - Renesas H8S Series Hardware Manual

Section 19 A/D Converter
19.3

Register Descriptions

The A/D converter has the following registers.
• A/D data register A (ADDRA)
• A/D data register B (ADDRB)
• A/D data register C (ADDRC)
• A/D data register D (ADDRD)
• A/D control/status register (ADCSR)
• A/D control register (ADCR)
19.3.1

A/D Data Registers A to D (ADDRA to ADDRD)

There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers which store a conversion result for each channel are shown
in table 19.2.
The 10-bit conversion data is stored in bits 15 to 6. The lower six bits are always read as 0.
The data bus between the CPU and A/D converter is eight bits wide. The upper byte can be read
directly from the CPU. However, when the lower byte is read from, data that was transferred to a
temporary register at reading of the upper byte is read. Accordingly, when reading from ADDR,
access in word units or access upper byte first, and then lower byte.

Table 19.2 Analog Input Channels and Corresponding ADDR

Analog Input Channel
Group 0
AN0
AN1
AN2
AN3
Rev. 3.00 Jul. 14, 2005 Page 720 of 986
REJ09B0098-0300
Group 1
AN4
AN5
AN6
AN7
A/D Data Register to Store A/D Conversion
Results
ADDRA
ADDRB
ADDRC
ADDRD