Output Compare Output Timing; Frc Clear Timing; Figure 11.5 Timing Of Output Compare A Output; Figure 11.6 Clearing Of Frc By Compare-Match A Signal - Renesas H8S Series Hardware Manual

11.5.2

Output Compare Output Timing

A compare-match signal occurs at the last state when the FRC and OCR values match (at the
timing when the FRC updates the counter value). When a compare-match signal occurs, the level
selected by the OLVL bit in TOCR is output at the output compare output pin (FTOA or FTOB).
Figure 11.5 shows the timing of this operation for compare-match A.
φ
FRC
OCRA
Compare-match
A signal
OLVLA
Output compare A
output pin FTOA
11.5.3

FRC Clear Timing

FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this
operation.
φ
Compare-match
A signal
FRC

Figure 11.6 Clearing of FRC by Compare-Match A Signal

N N + 1
N
Note : * Indicates instruction execution by software.

Figure 11.5 Timing of Output Compare A Output

N
Section 11 16-Bit Free-Running Timer (FRT)
N
Clear*
H'0000
Rev. 3.00 Jul. 14, 2005 Page 291 of 986
N + 1
N
REJ09B0098-0300